Fault tolerance architecture for reliable hybrid CMOS/nanodevices memory

NZB Haron, S Hamdioui

Research output: Contribution to conferencePosterProfessional

Original languageUndefined/Unknown
Publication statusPublished - 2009
EventETS'09 - Sevilla, Spanje
Duration: 25 May 200929 May 2009

Other

OtherETS'09
Period25/05/0929/05/09

Keywords

  • Geen BTA classificatie

Cite this

Haron, NZB., & Hamdioui, S. (2009). Fault tolerance architecture for reliable hybrid CMOS/nanodevices memory. Poster session presented at ETS'09, .