FPGA-based Deep Learning Accelerator for RF Applications

A key obstacle within the design of cognitive radios has always been the spectrum sensing component that implements the function automatic modulation classification (AMC). With the transition to software-defined radios (SDRs) followed by the introduction of field-programmable gate arrays (FPGAs) and deep learning (DL), it becomes possible to surmount this obstacle. However, the design of DL models is still detached from synthesized FPGA designs in current implementation frameworks. Consequently, the design process is a tedious and lengthy one. In this paper, a novel implementation framework is presented for implementing deep learning inference models within signal processing chains on FPGAs. The framework focuses on optimization for radio-frequency (RF) transceiver applications, aiming for high-throughput, low latency and a small FPGA resource footprint enabling the scaling to larger DL models. Demonstration of the implementation framework for automatic modulation classification (AMC) results in an operational throughput of 585k classifications per second.