Fractional spur suppression in all-digital phase-locked loops

P Chen; XC Huang; RB Staszewski

doi:10.1109/ISCAS.2015.7169209

Fractional spur suppression in all-digital phase-locked loops

Electronics

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

1 Citation (Scopus)

Original language	English
Title of host publication	Proceedings - 2015 IEEE International Symposium on Circuits and Systems
Editors	M de Medeiras Silva
Place of Publication	Piscataway, NJ, USA
Publisher	IEEE
Pages	2565-2568
Number of pages	4
ISBN (Print)	978-1-4799-8391-9
DOIs	https://doi.org/10.1109/ISCAS.2015.7169209
Publication status	Published - 2015
Event	IEEE ISCAS 2015: International symposium on circuits and systems - Piscataway, NJ, USA Duration: 24 May 2015 → 27 May 2015

Publication series

Name
Publisher	IEEE

Conference

Conference	IEEE ISCAS 2015
Period	24/05/15 → 27/05/15

Bibliographical note

Harvest

Access to Document

10.1109/ISCAS.2015.7169209

Cite this

@inproceedings{6f278a486f5140afa6a52ba459a2d52b,

title = "Fractional spur suppression in all-digital phase-locked loops",

author = "P Chen and XC Huang and RB Staszewski",

note = "Harvest; IEEE ISCAS 2015 : International symposium on circuits and systems ; Conference date: 24-05-2015 Through 27-05-2015",

year = "2015",

doi = "10.1109/ISCAS.2015.7169209",

language = "English",

isbn = "978-1-4799-8391-9",

publisher = "IEEE",

pages = "2565--2568",

editor = "{de Medeiras Silva}, M",

booktitle = "Proceedings - 2015 IEEE International Symposium on Circuits and Systems",

address = "United States",

}

Fractional spur suppression in all-digital phase-locked loops. / Chen, P; Huang, XC; Staszewski, RB.
Proceedings - 2015 IEEE International Symposium on Circuits and Systems. ed. / M de Medeiras Silva. Piscataway, NJ, USA: IEEE, 2015. p. 2565-2568.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

T1 - Fractional spur suppression in all-digital phase-locked loops

AU - Chen, P

AU - Huang, XC

AU - Staszewski, RB

N1 - Harvest

PY - 2015

Y1 - 2015

U2 - 10.1109/ISCAS.2015.7169209

DO - 10.1109/ISCAS.2015.7169209

M3 - Conference contribution

SN - 978-1-4799-8391-9

SP - 2565

EP - 2568

BT - Proceedings - 2015 IEEE International Symposium on Circuits and Systems

A2 - de Medeiras Silva, M

PB - IEEE

CY - Piscataway, NJ, USA

T2 - IEEE ISCAS 2015

Y2 - 24 May 2015 through 27 May 2015

ER -