Front to back-side 3D interconnects fabrication process based on controlled cu electroplating of high aspect ratio through silicon vias (HAR-TSVs)

M Saadaoui; WHA Wien; HW van Zeijl; H Schellevis; M Laros; PM Sarro

Front to back-side 3D interconnects fabrication process based on controlled cu electroplating of high aspect ratio through silicon vias (HAR-TSVs)

M Saadaoui, WHA Wien, HW van Zeijl, H Schellevis, M Laros, PM Sarro

Electronic Components, Technology and Materials

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

8 Citations (Scopus)

Original language	Undefined/Unknown
Title of host publication	10th electronics packaging technology conference
Editors	T Yang, T Kheng
Place of Publication	Singapore
Publisher	IEEE Society
Pages	219-223
Number of pages	5
ISBN (Print)	978-1-4244-2118-3
Publication status	Published - 2008
Event	EPTC 2008, Singapore - Singapore Duration: 9 Dec 2008 → 12 Dec 2008

Publication series

Name
Publisher	IEEE

Conference

Conference	EPTC 2008, Singapore
Period	9/12/08 → 12/12/08

Keywords

conference contrib. refereed
Conf.proc. > 3 pag

Cite this

@inproceedings{b48fbaac79aa46f8a0250a53cf9e7f62,

title = "Front to back-side 3D interconnects fabrication process based on controlled cu electroplating of high aspect ratio through silicon vias (HAR-TSVs)",

keywords = "conference contrib. refereed, Conf.proc. > 3 pag",

author = "M Saadaoui and WHA Wien and {van Zeijl}, HW and H Schellevis and M Laros and PM Sarro",

year = "2008",

language = "Undefined/Unknown",

isbn = "978-1-4244-2118-3",

publisher = "IEEE Society",

pages = "219--223",

editor = "T Yang and T Kheng",

booktitle = "10th electronics packaging technology conference",

note = "null ; Conference date: 09-12-2008 Through 12-12-2008",

}

Saadaoui, M, Wien, WHA , van Zeijl, HW , Schellevis, H, Laros, M & Sarro, PM 2008, Front to back-side 3D interconnects fabrication process based on controlled cu electroplating of high aspect ratio through silicon vias (HAR-TSVs). in T Yang & T Kheng (eds), 10th electronics packaging technology conference. IEEE Society, Singapore, pp. 219-223, EPTC 2008, Singapore, 9/12/08.

Front to back-side 3D interconnects fabrication process based on controlled cu electroplating of high aspect ratio through silicon vias (HAR-TSVs). / Saadaoui, M; Wien, WHA ; van Zeijl, HW ; Schellevis, H; Laros, M; Sarro, PM.

10th electronics packaging technology conference. ed. / T Yang; T Kheng. Singapore : IEEE Society, 2008. p. 219-223.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

T1 - Front to back-side 3D interconnects fabrication process based on controlled cu electroplating of high aspect ratio through silicon vias (HAR-TSVs)

AU - Saadaoui, M

AU - Wien, WHA

AU - van Zeijl, HW

AU - Schellevis, H

AU - Laros, M

AU - Sarro, PM

PY - 2008

Y1 - 2008

KW - conference contrib. refereed

KW - Conf.proc. > 3 pag

M3 - Conference contribution

SN - 978-1-4244-2118-3

SP - 219

EP - 223

BT - 10th electronics packaging technology conference

A2 - Yang, T

A2 - Kheng, T

PB - IEEE Society

CY - Singapore

Y2 - 9 December 2008 through 12 December 2008

ER -