Graphene-Based Complementary-Style Logic Gate with Memory-Lock

Nicoleta Cucu Laurenciu, Charles Timmermans, Nicolo De Groot, Sorin D. Cotofana

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

Abstract

As CMOS feature size vertiginously approaches atomic limits, high leakage and power density and exacer-bating IC production costs are prompting for development of new materials, devices, beyond von-Neumann architectures and computing paradigms. Within this context, graphene has emerged as a promising post-Si front runner, owing to its remarkable properties. In this paper, we propose a generic graphene-based complementary-style Boolean gate structure with memory-lock, that allows logic and non-volatile memory co-location. The gate with memory-lock is composed of 2 cells - a pull-up cell performing the gate Boolean function and a pull-down cell performing the inverted Boolean function. Each cell in turn, has a graphene logic layer that carries out Boolean gates computation, and a graphene memory layer for storing the logic state of the gate. As simulation vehicle we considered an inverter gate with memory-lock. Simulation results indicate a current ratio of write/read to/from memory of 1.64.102for gate input low, and of 2.55. 102for gate input high. Furthermore, the inverter with memory-lock exhibits a 128× smaller area footprint when compared to the traditional physically separate logic (e.g., 7nm inverter gate) and memory (e.g., 7nm 6T SRAM cell), establishing the potential of proposed structure with memory-lock for more compact and energy efficient future beyond CMOS nano-electronic implementations, and making it highly promising for high-density computations.

Original languageEnglish
Title of host publication2024 IEEE 24th International Conference on Nanotechnology, NANO 2024
PublisherIEEE
Pages586-591
Number of pages6
ISBN (Electronic)9798350386240
DOIs
Publication statusPublished - 2024
Event24th IEEE International Conference on Nanotechnology, NANO 2024 - Gijon, Spain
Duration: 8 Jul 202411 Jul 2024

Publication series

NameProceedings of the IEEE Conference on Nanotechnology
ISSN (Print)1944-9399
ISSN (Electronic)1944-9380

Conference

Conference24th IEEE International Conference on Nanotechnology, NANO 2024
Country/TerritorySpain
CityGijon
Period8/07/2411/07/24

Bibliographical note

Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care
Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.

Fingerprint

Dive into the research topics of 'Graphene-Based Complementary-Style Logic Gate with Memory-Lock'. Together they form a unique fingerprint.

Cite this