TY - JOUR
T1 - Hamiltonian phase error in resonantly driven CNOT gate above the fault-tolerant threshold
AU - Wu, Yi Hsien
AU - Camenzind, Leon C.
AU - Noiri, Akito
AU - Takeda, Kenta
AU - Nakajima, Takashi
AU - Kobayashi, Takashi
AU - Chang, Chien Yuan
AU - Sammak, Amir
AU - Scappucci, Giordano
AU - Tarucha, Seigo
PY - 2024
Y1 - 2024
N2 - Because of their long coherence time and compatibility with industrial foundry processes, electron spin qubits are a promising platform for scalable quantum processors. A full-fledged quantum computer will need quantum error correction, which requires high-fidelity quantum gates. Analyzing and mitigating gate errors are useful to improve gate fidelity. Here, we demonstrate a simple yet reliable calibration procedure for a high-fidelity controlled-rotation gate in an exchange-always-on Silicon quantum processor, allowing operation above the fault-tolerance threshold of quantum error correction. We find that the fidelity of our uncalibrated controlled-rotation gate is limited by coherent errors in the form of controlled phases and present a method to measure and correct these phase errors. We then verify the improvement in our gate fidelities by randomized benchmark and gate-set tomography protocols. Finally, we use our phase correction protocol to implement a virtual, high-fidelity, controlled-phase gate.
AB - Because of their long coherence time and compatibility with industrial foundry processes, electron spin qubits are a promising platform for scalable quantum processors. A full-fledged quantum computer will need quantum error correction, which requires high-fidelity quantum gates. Analyzing and mitigating gate errors are useful to improve gate fidelity. Here, we demonstrate a simple yet reliable calibration procedure for a high-fidelity controlled-rotation gate in an exchange-always-on Silicon quantum processor, allowing operation above the fault-tolerance threshold of quantum error correction. We find that the fidelity of our uncalibrated controlled-rotation gate is limited by coherent errors in the form of controlled phases and present a method to measure and correct these phase errors. We then verify the improvement in our gate fidelities by randomized benchmark and gate-set tomography protocols. Finally, we use our phase correction protocol to implement a virtual, high-fidelity, controlled-phase gate.
UR - http://www.scopus.com/inward/record.url?scp=85182163806&partnerID=8YFLogxK
U2 - 10.1038/s41534-023-00802-9
DO - 10.1038/s41534-023-00802-9
M3 - Article
AN - SCOPUS:85182163806
SN - 2056-6387
VL - 10
JO - NPJ Quantum Information
JF - NPJ Quantum Information
IS - 1
M1 - 8
ER -