Hardware-based aging mitigation scheme for memory address decoder

Daniel Kraak, Innocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Francky Catthoor

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

7 Citations (Scopus)
58 Downloads (Pure)


Designers typically add design margins to memories to compensate for their aging. As the aging impact increases with technology scaling, bigger margins become necessary. However, this negatively impacts area, yield, performance, and power consumption. Alternatively, mitigation schemes can be used to reduce the impact of aging. This paper proposes a hardware-based mitigation scheme for the memory's address decoder logic. The scheme is based on adapting the decoder's workload during idle cycles by stressing the short paths and putting long paths into relaxation. Thanks to the adapted workload, the impact of aging on the address decoder is reduced, resulting in a more reliable memory. To validate the benefit of the mitigation scheme, the decoder's degradation of the L1 data and instruction caches for an ARM v8-a processor is analyzed. The experimental results show that the proposed mitigation scheme reduces the degradation of the decoder's timing margin with up to 4.1x at negligible area and no more than 3% power overhead.
Original languageEnglish
Title of host publication2019 IEEE European Test Symposium (ETS)
Number of pages6
ISBN (Electronic)978-1-7281-1173-5
ISBN (Print)978-1-7281-1174-2
Publication statusPublished - 2019
Event24th IEEE European Test Symposium 2019 - Baden-Baden, Germany
Duration: 27 May 201931 May 2019
Conference number: 24th


Conference24th IEEE European Test Symposium 2019
Abbreviated titleETS
Internet address


  • Address decoder
  • Aging
  • Memory
  • Mitigation


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