High level Synthesis of Asynchronous Circuits from Data Flow Graphs

TGRM van Leuken, T (extern) Leeuwen, H Lincklaen Arriens

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

Original languageEnglish
Title of host publicationIntegrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation
EditorsJ Ayale et al
Place of PublicationBerlin Heidelberg
PublisherSpringer
Pages317-330
Number of pages14
ISBN (Print)978-3642- 24153-6
DOIs
Publication statusPublished - 2011
EventPATMOS 2011, Madrid, Spain - Berlin Heidelberg
Duration: 26 Sep 201129 Sep 2011

Publication series

Name
PublisherSpringer-Verlag
NameLecture Notes in Computer Science
Volume6951
ISSN (Print)0302-9743

Conference

ConferencePATMOS 2011, Madrid, Spain
Period26/09/1129/09/11

Keywords

  • CWTS JFIS < 0.75

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