High level Synthesis of Asynchronous Circuits from Data Flow Graphs

TGRM van Leuken; T (extern) Leeuwen; H Lincklaen Arriens

doi:10.1007/978-3-642-24153-3-32

High level Synthesis of Asynchronous Circuits from Data Flow Graphs

TGRM van Leuken, T (extern) Leeuwen, H Lincklaen Arriens

Circuits and Systems

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

Original language	English
Title of host publication	Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation
Editors	J Ayale et al
Place of Publication	Berlin Heidelberg
Publisher	Springer
Pages	317-330
Number of pages	14
ISBN (Print)	978-3642- 24153-6
DOIs	https://doi.org/10.1007/978-3-642-24153-3-32
Publication status	Published - 2011
Event	PATMOS 2011, Madrid, Spain - Berlin Heidelberg Duration: 26 Sep 2011 → 29 Sep 2011

Publication series

Name
Publisher	Springer-Verlag

Name	Lecture Notes in Computer Science
Volume	6951
ISSN (Print)	0302-9743

Conference

Conference	PATMOS 2011, Madrid, Spain
Period	26/09/11 → 29/09/11

Keywords

CWTS JFIS < 0.75

Access to Document

10.1007/978-3-642-24153-3-32

Cite this

van Leuken, TGRM., Leeuwen, T. ., & Lincklaen Arriens, H. (2011). High level Synthesis of Asynchronous Circuits from Data Flow Graphs. In J. Ayale et al (Ed.), Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation (pp. 317-330). (Lecture Notes in Computer Science; Vol. 6951). Springer. https://doi.org/10.1007/978-3-642-24153-3-32

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title = "High level Synthesis of Asynchronous Circuits from Data Flow Graphs",

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author = "{van Leuken}, TGRM and Leeuwen, {T (extern)} and {Lincklaen Arriens}, H",

year = "2011",

doi = "10.1007/978-3-642-24153-3-32",

language = "English",

isbn = "978-3642- 24153-6",

publisher = "Springer",

pages = "317--330",

editor = "{Ayale et al}, J",

booktitle = "Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation",

note = "PATMOS 2011, Madrid, Spain ; Conference date: 26-09-2011 Through 29-09-2011",

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van Leuken, TGRM, Leeuwen, T & Lincklaen Arriens, H 2011, High level Synthesis of Asynchronous Circuits from Data Flow Graphs. in J Ayale et al (ed.), Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation. Lecture Notes in Computer Science, vol. 6951, Springer, Berlin Heidelberg, pp. 317-330, PATMOS 2011, Madrid, Spain, 26/09/11. https://doi.org/10.1007/978-3-642-24153-3-32

High level Synthesis of Asynchronous Circuits from Data Flow Graphs. / van Leuken, TGRM; Leeuwen, T (extern); Lincklaen Arriens, H.

Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation. ed. / J Ayale et al. Berlin Heidelberg : Springer, 2011. p. 317-330 (Lecture Notes in Computer Science; Vol. 6951).

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

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AU - Lincklaen Arriens, H

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KW - CWTS JFIS < 0.75

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BT - Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation

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