Improved Dynamic Cache Sharing for Communicating Threads on a Runtime-Adaptable Processor

Joost Hoozemans, Arthur Lorenzon, Antonio Carlos Schneider Beck, Stephan Wong

Research output: Contribution to conferenceAbstractScientific

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Abstract—Multi-threaded applications execute their threads on different cores with their own local caches and need to share data among the threads. Shared caches are used to avoid lengthy and costly main memory accesses. The degree of cache sharing is a balance between reducing misses and increased hit latency.
Dynamic caches have been proposed to adapt this balance to the workload type. Similarly, dynamic processors aim to execute workloads as efficient as possible to being able to balance between exploiting Instruction-level parallelism (ILP) and Thread-level parallelism (TLP). To support this, they consist of multiple processing components and caches that have adaptable interconnects
between them. Depending on the workload characteristics, these can connect them together to form a large core that exploits ILP, or split them up to form multiple cores that can run multiple threads (exploiting TLP). In this paper, we propose a cache system that is able to further exploit this additional connectivity
of a dynamic VLIW processor by being able to forward cache accesses to multiple cache blocks while the processor is running in multi-threaded (‘split’) mode. Additionally, only requests to global data are broadcasted, while accesses to local data are kept private. This will improve the hit rates similar to existing cache
sharing schemes, but reduce the penalty due to stalling the other subcores. Local accesses are recognized by distinguishing memory accesses relative to the stack frame pointer. Results show that our cache exhibits similar miss rate reductions as shared caches (up to 90% and on average 26%), and reduces the number of
broadcasted accesses by 21%.
Original languageEnglish
Number of pages9
Publication statusPublished - Jan 2017
EventWorkshop Reconfigurable Computing 2017: 11th HiPEAC Workshop - HiPEAC 2017, Stockholm, Sweden
Duration: 23 Jan 201723 Jan 2017


WorkshopWorkshop Reconfigurable Computing 2017
Abbreviated titleWRC
Internet address


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