Improving the Detection of Undefined State Faults in FinFET SRAMs

G. Cardoso Medeiros, M. Fieback, Thiago Copetti, A.B. Gebregiorgis, M. Taouil, L. M. Bolzani Poehls, S. Hamdioui

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

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Abstract

Manufacturing defects in FinFET SRAMs can cause hard-to-detect faults such as Undefined State Faults (USFs). Detection of USFs is not trivial, as they may not lead to incorrect functionality. Nevertheless, undetected USFs may have a severe impact on the memory's quality: they can cause random read outputs, which might lead to test escapes and no-trouble-found devices later when the device is already in the field, as well as compromise the circuit's quality by reducing the memory cell's Static Noise Margin (SNM). Therefore, the detection of USF is critical. This paper proposes a test solution to improve the detection of USFs in FinFET SRAMs. To achieve this, we first analyze the impact of USFs on the cell's SNM and bitline swing during read operations. Then, we perform an experimental study of stress conditions' (SCs) impact on sensitizing and detecting USFs. Finally, we propose a dedicated Design-For-Testability (DFT) scheme for FinFET SRAMs to detect such faults. This scheme introduces a small area overhead while significantly improving USF detection. Hence, using the proposed DFT leads to fewer test escapes and higher-quality FinFET SRAMs.
Original languageEnglish
Title of host publicationInternational Conference on Design & Technology of Integrated System in Nanoscale Era (DTIS)
PublisherIEEE
Number of pages6
Edition16th
ISBN (Electronic)978-1-6654-3654-0
ISBN (Print)978-1-6654-3655-7
DOIs
Publication statusPublished - 2021
Event2021International Conference on Design & Technology of Integrated Systems in Nanoscale Era - Online, Apulia, Italy
Duration: 28 Jun 202130 Jun 2021
Conference number: 16
https://www.lirmm.fr/dtis2021/index.html#intro

Conference

Conference2021International Conference on Design & Technology of Integrated Systems in Nanoscale Era
Abbreviated titleDTIS
Country/TerritoryItaly
CityApulia
Period28/06/2130/06/21
Internet address

Keywords

  • Memory Testing
  • Undefined State
  • SRAM
  • FinFET
  • DFT

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