Manufacturing defects in FinFET SRAMs can cause hard-to-detect faults such as Undefined State Faults (USFs). Detection of USFs is not trivial, as they may not lead to incorrect functionality. Nevertheless, undetected USFs may have a severe impact on the memory's quality: they can cause random read outputs, which might lead to test escapes and no-trouble-found devices later when the device is already in the field, as well as compromise the circuit's quality by reducing the memory cell's Static Noise Margin (SNM). Therefore, the detection of USF is critical. This paper proposes a test solution to improve the detection of USFs in FinFET SRAMs. To achieve this, we first analyze the impact of USFs on the cell's SNM and bitline swing during read operations. Then, we perform an experimental study of stress conditions' (SCs) impact on sensitizing and detecting USFs. Finally, we propose a dedicated Design-For-Testability (DFT) scheme for FinFET SRAMs to detect such faults. This scheme introduces a small area overhead while significantly improving USF detection. Hence, using the proposed DFT leads to fewer test escapes and higher-quality FinFET SRAMs.
|Title of host publication||International Conference on Design & Technology of Integrated System in Nanoscale Era|
|Number of pages||6|
|Publication status||Accepted/In press - Jun 2021|
- Memory Testing
- Undefined State