Incorporating Parameter Variations in BTI Impact on Nano-scale Logical Gates Analysis

MSK Seyab, S Hamdioui, H Kukner, P Raghavan, F Catthoor

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

9 Citations (Scopus)
Original languageEnglish
Title of host publicationIEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems
Editors s.n.
Place of PublicationNew York
PublisherIEEE Society
Pages1-6
Number of pages6
Publication statusPublished - 2012
EventDFT 2012/Austin USA - New York
Duration: 3 Oct 20125 Oct 2012

Publication series

Name
PublisherIEEE

Conference

ConferenceDFT 2012/Austin USA
Period3/10/125/10/12

Cite this

Seyab, MSK., Hamdioui, S., Kukner, H., Raghavan, P., & Catthoor, F. (2012). Incorporating Parameter Variations in BTI Impact on Nano-scale Logical Gates Analysis. In s.n. (Ed.), IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (pp. 1-6). IEEE Society.