TY - JOUR
T1 - Integral Impact of BTI, PVT Variation, and Workload on SRAM Sense Amplifier
AU - Agbo, Innocent
AU - Taouil, Mottaqiallah
AU - Kraak, Daniël
AU - Hamdioui, Said
AU - Kükner, H.
AU - Weckx, Pieter
AU - Raghavan, Praveen
AU - Catthoor, Francky
PY - 2017
Y1 - 2017
N2 - The CMOS technology scaling faced over the past recent decades severe variability and reliability challenges. One of the major reliability challenges is bias temperature instability (BTI). This paper analyzes the impact of BTI on the sensing delay of standard latch-type sense amplifier (SA), which is one of the critical components of high performance memories; the analysis is done by incorporating the impact of process, voltage, and temperature variations (in order to investigate the severity of the integral impact) and by considering different workloads and four technology nodes (i.e., 45, 32, 22, and 16 nm). The results show the importance of taking the SA degradation into consideration for robust memory design; the SA degradation depends on the application and technology node, and the sensing delay can increase with 184.58% for the worst case conditions at 16 nm. The results also show that the BTI impact for nominal conditions at 16 nm reaches a 12.10% delay increment. On top of that, when extrinsic conditions are considered, the degradation can reach up to 168.45% at 398 K for 16 nm.
AB - The CMOS technology scaling faced over the past recent decades severe variability and reliability challenges. One of the major reliability challenges is bias temperature instability (BTI). This paper analyzes the impact of BTI on the sensing delay of standard latch-type sense amplifier (SA), which is one of the critical components of high performance memories; the analysis is done by incorporating the impact of process, voltage, and temperature variations (in order to investigate the severity of the integral impact) and by considering different workloads and four technology nodes (i.e., 45, 32, 22, and 16 nm). The results show the importance of taking the SA degradation into consideration for robust memory design; the SA degradation depends on the application and technology node, and the sensing delay can increase with 184.58% for the worst case conditions at 16 nm. The results also show that the BTI impact for nominal conditions at 16 nm reaches a 12.10% delay increment. On top of that, when extrinsic conditions are considered, the degradation can reach up to 168.45% at 398 K for 16 nm.
KW - Bias temperature instability (BTI)
KW - negative BTI (NBTI)
KW - positive BTI (PBTI)
KW - process variations
KW - static RAM (SRAM) sense amplifier (SA)
UR - http://www.scopus.com/inward/record.url?scp=85010015848&partnerID=8YFLogxK
U2 - 10.1109/TVLSI.2016.2643618
DO - 10.1109/TVLSI.2016.2643618
M3 - Article
AN - SCOPUS:85010015848
SN - 1063-8210
VL - 25
SP - 1444
EP - 1454
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 4
M1 - 7819518
ER -