Integral Impact of BTI, PVT Variation, and Workload on SRAM Sense Amplifier

Innocent Agbo, Mottaqiallah Taouil, Daniël Kraak, Said Hamdioui, H. Kükner, Pieter Weckx, Praveen Raghavan, Francky Catthoor

Research output: Contribution to journalArticleScientificpeer-review

35 Citations (Scopus)


The CMOS technology scaling faced over the past recent decades severe variability and reliability challenges. One of the major reliability challenges is bias temperature instability (BTI). This paper analyzes the impact of BTI on the sensing delay of standard latch-type sense amplifier (SA), which is one of the critical components of high performance memories; the analysis is done by incorporating the impact of process, voltage, and temperature variations (in order to investigate the severity of the integral impact) and by considering different workloads and four technology nodes (i.e., 45, 32, 22, and 16 nm). The results show the importance of taking the SA degradation into consideration for robust memory design; the SA degradation depends on the application and technology node, and the sensing delay can increase with 184.58% for the worst case conditions at 16 nm. The results also show that the BTI impact for nominal conditions at 16 nm reaches a 12.10% delay increment. On top of that, when extrinsic conditions are considered, the degradation can reach up to 168.45% at 398 K for 16 nm.

Original languageEnglish
Article number7819518
Pages (from-to)1444-1454
Number of pages11
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number4
Publication statusPublished - 2017


  • Bias temperature instability (BTI)
  • negative BTI (NBTI)
  • positive BTI (PBTI)
  • process variations
  • static RAM (SRAM) sense amplifier (SA)


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