Integrator delay zero model for design of upstream water-level controllers

A variety of methods are in use for the design of controllers for adjusting canal gate positions to maintain a constant water level immediately upstream from check gates. These methods generally rely on a series of tests on the water level's response to changes in canal gate position or flow, either by simulation or on the canal itself. This paper presents a method for tuning these controllers based on wave celerity through use of the integrator delay zero (IDZ) model. These equations can be used to determine the resonance peak height and resonance frequency. Unsteady-flow canal simulation models are used to show the response of controller design using these theoretical equations with a test case for ASCE Test Canal 1. A novel method is presented for avoiding disturbance amplification by considering the delay times in all canal pools downstream.