Intermittent Undefined State Fault in RRAMs

Moritz Fieback, Guilherme Cardoso Medeiros, Anteneh Gebregiorgis, Hassen Aziza, Mottaqiallah Taouil, Said Hamdioui

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

10 Citations (Scopus)
33 Downloads (Pure)

Abstract

Industry is prototyping and commercializing Resistive Random Access Memories (RRAMs). Unfortunately, RRAM devices introduce new defects and faults. Hence, high-quality test solutions are urgently needed. Based on silicon measurements, this paper identifies a new RRAM unique fault, the Intermittent Undefined State Fault (IUSF); this fault causes the RRAM device to intermittently change its switching mechanism from bipolar to complementary switching, resulting in undefined state faults. First, we characterize the IUSF by analyzing RRAM devices, and demonstrate that a single RRAM device can suffer from the IUSF up to 1.068 % of its switching cycles; we relate the IUSF to two defects: capping layer doping, and over-forming. This clearly shows the importance of detecting this fault. Second, we develop a device-aware defect model that accurately describes the physical behavior of these defects and gives essential insights into the IUSF’s behavior and its detection. Third, we perform fault modeling by applying the device-aware defect model, and the results are used to develop high-quality test solutions for the IUSF. The contributions in this work improve the overall RRAM test quality, which enables mass commercialization of RRAMs
Original languageEnglish
Title of host publication2021 IEEE European Test Symposium (ETS)
Place of PublicationDanvers
PublisherIEEE
Number of pages6
ISBN (Electronic)978-1-6654-1849-2
ISBN (Print)978-1-6654-4819-2
DOIs
Publication statusPublished - 2021
Event2021 IEEE European Test Symposium (ETS) - Virtual at Bruges, Belgium
Duration: 24 May 202128 May 2021

Conference

Conference2021 IEEE European Test Symposium (ETS)
Country/TerritoryBelgium
CityVirtual at Bruges
Period24/05/2128/05/21

Keywords

  • RRAM test
  • defect modeling
  • device-aware test

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