ISA-DTMR: Selective Protection in Configurable Heterogeneous Multicores

Augusto G. Erichsen, Anderson L. Sartor, Jeckson D. Souza, Monica M. Pereira, Stephan Wong, Antonio C.S. Beck

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

1 Citation (Scopus)


The well-known Triple Modular Redundancy (TMR), when applied to processors to mitigate the occurrence of faults, implies that all applications have the same level of criticality (since they are all equally protected) and are executed in a homogeneous environment, which naturally would waste precious resources in terms of area and energy. However, many current systems are composed of heterogeneous cores that implement the same ISA (e.g., ARM’s big.LITTLE or DynamIQ), executing some applications that may be more critical than others and that would require different levels of protection. With that in mind, we propose ISA-DTMR, a non-intrusive approach that, taking advantage of heterogeneous systems, can protect applications at different levels in a totally transparent fashion. By using heterogeneous multicore configurations composed of configurable processors that implement the same Instruction Set Architecture (ISA), we will show that it is possible to adapt the level of protection for each application according to its reliability requirements. When compared to homogeneous processors, ISA-DTMR reduces area by up to 54.9%, and energy consumption by 30.35%, with negligible overhead on performance, for a configuration that balances performance and energy consumption. ISA-DTMR is able to provide the same level of protection for critical applications and even improve the reliability for non-critical applications.

Original languageEnglish
Title of host publicationApplied Reconfigurable Computing
Subtitle of host publicationArchitectures, Tools, and Applications - 14th International Symposium, ARC 2018, Proceedings
EditorsN. Voros, M. Huebner, G. Keramidas, D. Goehringer, C. Antonpoulos, P.C. Diniz
Place of PublicationCham
Number of pages12
ISBN (Electronic)978-3-319-7889-6
ISBN (Print)978-3-319-78889-0
Publication statusPublished - 2018
EventARC 2018: 14th International Symposium on Applied Reconfigurable Computing - Santorini, Greece
Duration: 2 May 20184 May 2018

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349


ConferenceARC 2018


  • Fault tolerance
  • Heterogeneous architecture
  • TMR
  • DMR


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