Logical effort based design exploration of 64-bit adders using a mixed dynamic-CMOS/Threshold-logic approach

P Celinski, S Al-Sarawi, D Abbott, SD Cotofana, S Vassiliadis

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

5 Citations (Scopus)
Original languageUndefined/Unknown
Title of host publicationProceedings IEEE Computer Society annual symposium on VLSI; Emerging trends in VLSI systems design
EditorsA Smailagic, M Bayoumi
Place of PublicationLos Alamitos
PublisherIEEE
Pages127-132
Number of pages6
ISBN (Print)0-7695-2097-9
Publication statusPublished - 2004
EventIEEE Computer Society annual symposium on VLSI; Emerging trends in VLSI systems design, Lafayette, USA - Los Alamitos
Duration: 19 Feb 200420 Feb 2004

Publication series

Name
PublisherIEEE Computer Society

Conference

ConferenceIEEE Computer Society annual symposium on VLSI; Emerging trends in VLSI systems design, Lafayette, USA
Period19/02/0420/02/04

Keywords

  • conference contrib. refereed
  • Conf.proc. > 3 pag

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