Logical effort delay modeling of sense amplifier based charge recycling threshold logic gates

P Celinski, SD Cotofana, D Abbott

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

Original language	Undefined/Unknown
Title of host publication	Proceedings of ProRISC 2003
Editors	s.n.
Place of Publication	Utrecht
Publisher	STW
Pages	43-48
Number of pages	6
ISBN (Print)	90-73461-39-1
Publication status	Published - 2003
Event	ProRISC 2003, Veldhoven, The Netherlands - Utrecht Duration: 26 Nov 2003 → 27 Nov 2003

Name
Publisher	STW

Conference	ProRISC 2003, Veldhoven, The Netherlands
Period	26/11/03 → 27/11/03

Keywords

@inproceedings{f283379c9fd041fd94f98804009aedd5,

title = "Logical effort delay modeling of sense amplifier based charge recycling threshold logic gates",

keywords = "Elektrotechniek, Techniek, Vakpubl., Overig wet. > 3 pag",

author = "P Celinski and SD Cotofana and D Abbott",

year = "2003",

language = "Undefined/Unknown",

isbn = "90-73461-39-1",

publisher = "STW",

pages = "43--48",

editor = "s.n.",

booktitle = "Proceedings of ProRISC 2003",

note = "null ; Conference date: 26-11-2003 Through 27-11-2003",

}

TY - GEN

T1 - Logical effort delay modeling of sense amplifier based charge recycling threshold logic gates

AU - Celinski, P

AU - Cotofana, SD

AU - Abbott, D

PY - 2003

Y1 - 2003

KW - Elektrotechniek

KW - Techniek

KW - Vakpubl., Overig wet. > 3 pag

M3 - Conference contribution

SN - 90-73461-39-1

SP - 43

EP - 48

BT - Proceedings of ProRISC 2003

A2 - s.n., null

PB - STW

CY - Utrecht

Y2 - 26 November 2003 through 27 November 2003

ER -