Low cost multi-error correction for 3D polyhedral memories

Mihai Lefter, Thomas Marconi, George Voicu, Sorin Cotofana

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

1 Citation (Scopus)


In this paper we propose a novel error correction scheme/architecture specially tailored for polyhedral memories which: (i) allows for the formation of long codewords without interfering with the memory architecture/addressing mode/data granularity and (ii) make use of codecs located on a dedicated tier of the 3D memory stack. For a transparent error correction process we propose an online memory scrubbing policy that performs the error detection and correction decoupled from the normal memory operation. To evaluate our proposal we consider as a case study a 4-die 4-MB polyhedral memory and simulate various data width codes implementations. The simulations indicate that our proposal outperforms state of the art single error correction schemes in terms of error correction capability, being able to diminish the Word Error Rates (WER) by many orders of magnitude, e.g., WER from 10-10 to 10-21 are achieved for bit error probabilities between 10-4 and 10-6, while requiring less redundancy overhead. The scrubbing mechanism hides the codec latency and provides up to 10% and 25% write and read latency reductions, respectively. In addition, by relocating the encoders/decoders from the memory dies to a dedicated one a 13% footprint reduction is obtained and parallel energy effective scrubbing can be enabled, which results in further WER reductions.

Original languageEnglish
Title of host publication2017 IEEE/ACM International Symposium on Nanoscale Architectures
Number of pages6
ISBN (Electronic)978-1-5090-6037-5
ISBN (Print)978-1-5090-6038-2
Publication statusPublished - 2017
Event2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) - Newport, United States
Duration: 25 Jul 201726 Jul 2017


Conference2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)
Abbreviated title2017
CountryUnited States


  • Error correction codes
  • Error correction
  • Codecs
  • Proposals
  • Trhough-Silicon vias
  • Maintenance engineering
  • Three-dimensional displays

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