Mapping of Lattice Surgery-based Quantum Circuits on Surface Code Architectures

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Abstract

Quantum error correction (QEC) and fault-tolerant (FT) mechanisms are essential for reliable quantum computing. However, QEC considerably increases the computation size up to four orders of magnitude. Moreover, FT implementation has specific requirements on qubit layouts, causing both resource and time overhead. Reducing spatial-temporal costs becomes critical since it is beneficial to decrease the failure rate of quantum computation. To this purpose, scalable qubit plane architectures and efficient mapping passes including placement and routing of qubits as well as scheduling of operations are needed. This paper proposes a full mapping process to execute lattice surgery-based quantum circuits on two surface code architectures, namely a checkerboard and a tile-based one. We show that the checkerboard architecture is 2x qubit-efficient but the tile-based one requires lower communication overhead in terms of both operation overhead (up to 86%) and latency overhead (up to 79%).
Original languageEnglish
Article number015005
Pages (from-to)1-20
Number of pages20
JournalQuantum Science and Technology
Volume4
Issue number1
DOIs
Publication statusPublished - 2019

Keywords

  • lattice surgery
  • operation scheduling
  • quantum computing
  • qubit placement and routing
  • qubit plane architecture
  • surface code

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