Abstract
Short and efficient memory tests is the goal of every test designer. To reduce the cost of production tests, often a simple test which covers most of the faults, e.g. all simple (unlinked) faults, is desirable to eliminate most defective parts; a more costly test can be used thereafter to eliminate the remainder of the bad parts. Such a test-cost efficient approach is used by most manufacturers. In addition, system power-on tests are not allowed a long test time while a high fault coverage is desirable. The authors propose a new realistic fault model (the disturb fault model), and a set of tests for unlinked faults. These tests have the property of covering all simple (unlinked) faults at a very reasonable test time compared with existing tests.
| Original language | English |
|---|---|
| Pages (from-to) | 155-160 |
| Number of pages | 6 |
| Journal | IEE Proceedings: Circuits, Devices and Systems |
| Volume | 144 |
| Issue number | 3 |
| DOIs | |
| Publication status | Published - 1997 |
Keywords
- Disturb fault
- Fault model
- March tests
- Memory faillis
- Memory tests
- Simple faults
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