Memory mapping for multi-die FPGAS

Nils Voss, Pablo Quintana, Oskar Mencer, Wayne Luk, Georgi Gaydadjiev

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

Abstract

This paper proposes an algorithm for mapping logical to physical memory resources on FPGAs. Our greedy strategy based algorithm is specifically designed to facilitate timing closure on modern multi-die FPGAs for static-dataflow accelerators utilising most of the on-chip resources. The main objective of the proposed algorithm is to ensure that specific sub-parts of the design under consideration can fully reside within a single die to limit inter-die communication. The above is achieved by performing the memory mapping for each sub-part of the design separately while keeping allocation of the available physical resources balanced. As a result the number of inter-die connections is reduced on average by 50% compared to an algorithm targeting minimal area usage for real, complex applications using most of the on-chip's resources. Additionally, our algorithm is the only one out of the four evaluated approaches which successfully produces place and route results for all 33 applications and benchmarks.

Original languageEnglish
Title of host publicationProceedings - 27th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2019
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages78-86
Number of pages9
ISBN (Electronic)9781728111315
DOIs
Publication statusPublished - 1 Apr 2019
Externally publishedYes
Event27th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2019 - San Diego, United States
Duration: 28 Apr 20191 May 2019

Publication series

NameAnnual IEEE Symposium on Field-Programmable Custom Computing Machines

Conference

Conference27th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2019
CountryUnited States
CitySan Diego
Period28/04/191/05/19

Keywords

  • FPGA
  • Greedy Heuristic
  • Memory Allocation
  • Memory Mapping
  • Multi Die

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  • Cite this

    Voss, N., Quintana, P., Mencer, O., Luk, W., & Gaydadjiev, G. (2019). Memory mapping for multi-die FPGAS. In Proceedings - 27th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2019 (pp. 78-86). [8735557] (Annual IEEE Symposium on Field-Programmable Custom Computing Machines). Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/FCCM.2019.00021