MEMS-Electronics Integration 2: A Smart Temperature Sensor for an Organ-on-a-chip Platform

In this work, an in-situ smart temperature sensor is designed and monolithically integrated in an organon-a-chip (OOC) platform. This will allow a non-incubator temperature monitoring, besides a more accurate temperature measurement of the cell culture. The custom, simple, robust and flexible IC technology used for the sensor fabrication grants a very cost-effective integrated solution in virtue of the reduced cost per wafer along with the large silicon area available in the platform. The circuit comprises a PTAT generator that periodically feeds a current controlled oscillator to produce a digitally-represented signal. The temperature information depends on this feeding periodicity, therefore, it is encoded in the time domain. The periodic switching activity is controlled by the output of the comparator and the first buffer stage. The output can be interfaced with a microcontroller for further post-processing. The fabrication used a “MEMS-last” process to avoid potential PDMS and other material contamination. A planar BiCMOS IC technology that requires only 7 masks steps is used to fabricate NPN and n/p-MOSFET transistors. A double-polished p-type silicon wafer was used. Mask 1 defines the n-well and the collector area of the NPN transistor, while masks 2 and 3 define, respectively, the n/p-type diffusion areas for the CMOS and the emitter/base area for the bipolar device. Contact openings are wet etched after the patterning of mask 4, while mask 5 is used to pattern the interconnect and gate material via deposition of AlSi. Masks 6 and 7 are used to open vias and deposit the second metallization. This last step is also used to deposit the first metallization of the OOC. The process follows with the SiO2 deposition using PECVD on the front and back of the wafer. The SiO2 layer on the back is dry etched to define the membrane area. PDMS is spun onto the front of the wafer and cured for 30 min at 90 °C. Finally, the membrane is released removing the Si and the SiO2 layers from underneath the membrane using DRIE and BHF, respectively. Wafer level measurements confirms the functionality of the circuit.