Designers typically add design margins to semiconductor memories to compensate for aging. However, the aging impact increases with technology downscaling, leading to the need for higher margins. This results into a negative impact on area, yield, performance, and power consumption. As an alternative, mitigation schemes can be developed to reduce such impact. This paper proposes a mitigation scheme for the memory's sense amplifier (SA); the scheme is based on creating a skew in the relative strengths of the SA's cross-coupled inverters during design. The skew is compensated by aging due to unbalanced workloads. As a result, the impact of aging on the SA is reduced. To validate the mitigation scheme, the degradation of the sense amplifier is analyzed for several workloads. The experimental results show that the proposed mitigation scheme reduces the degradation of the sense amplifier's critical figure-of-merit, the offset voltage, with up to 26%.
|Title of host publication||Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020|
|Editors||Giorgio Di Natale, Cristiana Bolchini, Elena-Ioana Vatajelu|
|Publisher||Institute of Electrical and Electronics Engineers (IEEE)|
|Number of pages||4|
|Publication status||Published - Mar 2020|
|Event||2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020 - Grenoble, France|
Duration: 9 Mar 2020 → 13 Mar 2020
|Name||Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020|
|Conference||2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020|
|Period||9/03/20 → 13/03/20|
|Other||Because of the COVID-19 outbreak, the conference took place in a virtual environment, in April and May 2020.|
Bibliographical noteBecause of the COVID-19 outbreak, the conference took place in a virtual environment, in April and May 2020.
- sense amplifier