Modeling Soft-Error Reliability Under Variability

Aneesh Balakrishnan; G. Cardoso Medeiros; Cemil Cem Gursoy; S. Hamdioui; Maksim Jenihhin; Dan Alexandrescu

doi:10.1109/DFT52944.2021.9568295

Modeling Soft-Error Reliability Under Variability

Aneesh Balakrishnan, G. Cardoso Medeiros, Cemil Cem Gursoy, S. Hamdioui, Maksim Jenihhin, Dan Alexandrescu

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

1 Citation (Scopus)

51 Downloads (Pure)

Abstract

The Soft-Error (SE) reliability and the effects of Negative Bias Temperature Instability (NBTI) in deep submicron technologies are characterized as the major critical issues of high-performance integrated circuits. The previous scientific research studies provide a comprehensive description that the soft-error vulnerability becomes more severe as the circuit performance degrades with aging. The main reason is the reduction of cell-level critical charge in an aging environment. However, such increased soft-error generation does not necessarily contribute towards circuits' critical functional failures. The proposal of this paper is the experimental investigation of soft error propagation at the aged gate-level by considering the different derating factors like Electrical Derating (EDR), Temporal Derating (TDR), Logical Derating (LDR), and Functional Derating (FDR). As contrary to the previous studies, the results of this work prove that SEU fault propagation probability is reducing in critical paths as time advances while the propagation probability of SET faults is neither reducing nor increasing, but the spot of generation of failure enhancing SETs is shifting within the clock period.

Original language	English
Title of host publication	34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Publisher	IEEE
Pages	1-6
Number of pages	6
ISBN (Electronic)	978-1-6654-1609-2
DOIs	https://doi.org/10.1109/DFT52944.2021.9568295
Publication status	Published - 2021
Event	34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems - Online, Athens, Greece Duration: 6 Oct 2021 → 8 Oct 2021 Conference number: 34 http://www.dfts.org/

Conference

Conference	34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems
Abbreviated title	DFT 2021
Country/Territory	Greece
City	Athens
Period	6/10/21 → 8/10/21
Internet address	http://www.dfts.org/

Keywords

NBTI
Standard Delay Format
Single Event Upset
Single Event Transient

Access to Document

10.1109/DFT52944.2021.9568295

DFTS2021_SOFT_AGINGAccepted author manuscript, 2.06 MB

https://www.computer.org/csdl/proceedings-article/dft/2021/09568295/1xPsvsEBkxq

Cite this

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title = "Modeling Soft-Error Reliability Under Variability",

abstract = "The Soft-Error (SE) reliability and the effects of Negative Bias Temperature Instability (NBTI) in deep submicron technologies are characterized as the major critical issues of high-performance integrated circuits. The previous scientific research studies provide a comprehensive description that the soft-error vulnerability becomes more severe as the circuit performance degrades with aging. The main reason is the reduction of cell-level critical charge in an aging environment. However, such increased soft-error generation does not necessarily contribute towards circuits' critical functional failures. The proposal of this paper is the experimental investigation of soft error propagation at the aged gate-level by considering the different derating factors like Electrical Derating (EDR), Temporal Derating (TDR), Logical Derating (LDR), and Functional Derating (FDR). As contrary to the previous studies, the results of this work prove that SEU fault propagation probability is reducing in critical paths as time advances while the propagation probability of SET faults is neither reducing nor increasing, but the spot of generation of failure enhancing SETs is shifting within the clock period.",

keywords = "NBTI, Standard Delay Format, Single Event Upset, Single Event Transient",

author = "Aneesh Balakrishnan and {Cardoso Medeiros}, G. and {Cem Gursoy}, Cemil and S. Hamdioui and Maksim Jenihhin and Dan Alexandrescu",

year = "2021",

doi = "10.1109/DFT52944.2021.9568295",

language = "English",

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booktitle = "34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)",

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}

Balakrishnan, A, Cardoso Medeiros, G, Cem Gursoy, C, Hamdioui, S, Jenihhin, M & Alexandrescu, D 2021, Modeling Soft-Error Reliability Under Variability. in 34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT). IEEE , pp. 1-6, 34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Athens, Greece, 6/10/21. https://doi.org/10.1109/DFT52944.2021.9568295

Modeling Soft-Error Reliability Under Variability. / Balakrishnan, Aneesh; Cardoso Medeiros, G.; Cem Gursoy, Cemil et al.

34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT). IEEE , 2021. p. 1-6.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

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AU - Cardoso Medeiros, G.

AU - Cem Gursoy, Cemil

AU - Hamdioui, S.

AU - Jenihhin, Maksim

AU - Alexandrescu, Dan

N1 - Conference code: 34

PY - 2021

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N2 - The Soft-Error (SE) reliability and the effects of Negative Bias Temperature Instability (NBTI) in deep submicron technologies are characterized as the major critical issues of high-performance integrated circuits. The previous scientific research studies provide a comprehensive description that the soft-error vulnerability becomes more severe as the circuit performance degrades with aging. The main reason is the reduction of cell-level critical charge in an aging environment. However, such increased soft-error generation does not necessarily contribute towards circuits' critical functional failures. The proposal of this paper is the experimental investigation of soft error propagation at the aged gate-level by considering the different derating factors like Electrical Derating (EDR), Temporal Derating (TDR), Logical Derating (LDR), and Functional Derating (FDR). As contrary to the previous studies, the results of this work prove that SEU fault propagation probability is reducing in critical paths as time advances while the propagation probability of SET faults is neither reducing nor increasing, but the spot of generation of failure enhancing SETs is shifting within the clock period.

AB - The Soft-Error (SE) reliability and the effects of Negative Bias Temperature Instability (NBTI) in deep submicron technologies are characterized as the major critical issues of high-performance integrated circuits. The previous scientific research studies provide a comprehensive description that the soft-error vulnerability becomes more severe as the circuit performance degrades with aging. The main reason is the reduction of cell-level critical charge in an aging environment. However, such increased soft-error generation does not necessarily contribute towards circuits' critical functional failures. The proposal of this paper is the experimental investigation of soft error propagation at the aged gate-level by considering the different derating factors like Electrical Derating (EDR), Temporal Derating (TDR), Logical Derating (LDR), and Functional Derating (FDR). As contrary to the previous studies, the results of this work prove that SEU fault propagation probability is reducing in critical paths as time advances while the propagation probability of SET faults is neither reducing nor increasing, but the spot of generation of failure enhancing SETs is shifting within the clock period.

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KW - Standard Delay Format

KW - Single Event Upset

KW - Single Event Transient

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PB - IEEE

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Y2 - 6 October 2021 through 8 October 2021

ER -

Modeling Soft-Error Reliability Under Variability

Abstract

Conference

Keywords

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DFT'21 Outstanding Student Paper

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Modeling Soft-Error Reliability Under Variability

Abstract

Conference

Keywords

Access to Document

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Prizes

DFT'21 Outstanding Student Paper

Cite this