Modeling Static Noise Margin for FinFET based SRAM PUFs

Shayesteh Masoumian, Georgios Selimis, Roel Maes, Geert-Jan Schrijen, Said Hamdioui, Mottaqiallah Taouil

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

4 Citations (Scopus)
208 Downloads (Pure)


In this paper, we develop an analytical PUF model based on a compact FinFET transistor model that calculates the PUF stability (i.e. PUF static noise margin (PSNM)) for FinFET based SRAMs. The model enables a quick design space exploration and may be used to identify critical parameters that affect the PSNM. The analytical model is validated with SPICE simulations. In our experiments, we analyze the impact of process variation, technology, and temperature on the PSNM. The results show that the analytical model matches very well with the simulation model. From the experiments we conclude the following: (1) nFET variations have a larger impact on the PSNM than pFET (1.5% higher PSNM in nFET variations than pFET variations at 25°C), (2) high performance SRAM cells are more skewed (1.3% higher PSNM) (3) the reproducibility increases with smaller technology nodes (0.8% PSNM increase from 20 to 14 nm) (4) increasing the temperature from-10°C to 120°C leads to a PSNM change of approximately 1.0% for an extreme nFET channel length.

Original languageEnglish
Title of host publication2020 IEEE European Test Symposium (ETS)
Subtitle of host publicationProceedings
Number of pages6
ISBN (Electronic)978-1-7281-4312-5
ISBN (Print)978-1-7281-4313-2
Publication statusPublished - 2020
EventETS 2020: 2020 IEEE European Test Symposium - Tallinn, Estonia
Duration: 25 May 202029 May 2020


ConferenceETS 2020

Bibliographical note

Accepted author manuscript


  • FinFET
  • process variation
  • Static noise margin
  • temperature


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