Multilayer VLSI layout for interconnection networks

CH Yeh, EA Varvarigos, B Parhami

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific

Original language	Undefined/Unknown
Title of host publication	ICPP 2000 proceedings
Editors	DJ Lilja
Place of Publication	Los Alamitos
Publisher	IEEE
Pages	33-40
Number of pages	8
ISBN (Print)	0-7695-0768-9
Publication status	Published - 2000
Event	2000 International Conference on Parallel Processing, Toronto - Los Alamitos Duration: 21 Aug 2000 → 24 Aug 2000

Name
Publisher	IEEE Computer Society

Conference	2000 International Conference on Parallel Processing, Toronto
Period	21/08/00 → 24/08/00

Cite this

Yeh, CH., Varvarigos, EA., & Parhami, B. (2000). Multilayer VLSI layout for interconnection networks. In DJ Lilja (Ed.), ICPP 2000 proceedings (pp. 33-40). IEEE.

@inproceedings{71d5d738bfd543889fee0d047003f53f,

title = "Multilayer VLSI layout for interconnection networks",

keywords = "ZX Int.klas.verslagjaar < 2002",

author = "CH Yeh and EA Varvarigos and B Parhami",

year = "2000",

language = "Undefined/Unknown",

isbn = "0-7695-0768-9",

publisher = "IEEE",

pages = "33--40",

editor = "{DJ Lilja}",

booktitle = "ICPP 2000 proceedings",

address = "United States",

note = "null ; Conference date: 21-08-2000 Through 24-08-2000",

}