Multilayer VLSI layout for interconnection networks

CH Yeh, EA Varvarigos, B Parhami

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

22 Citations (Scopus)
Original languageUndefined/Unknown
Title of host publicationICPP 2000 proceedings
Editors DJ Lilja
Place of PublicationLos Alamitos
PublisherIEEE
Pages33-40
Number of pages8
ISBN (Print)0-7695-0768-9
Publication statusPublished - 2000
Event2000 International Conference on Parallel Processing, Toronto - Los Alamitos
Duration: 21 Aug 200024 Aug 2000

Publication series

Name
PublisherIEEE Computer Society

Conference

Conference2000 International Conference on Parallel Processing, Toronto
Period21/08/0024/08/00

Keywords

  • ZX Int.klas.verslagjaar < 2002

Cite this

Yeh, CH., Varvarigos, EA., & Parhami, B. (2000). Multilayer VLSI layout for interconnection networks. In DJ Lilja (Ed.), ICPP 2000 proceedings (pp. 33-40). IEEE.