Multiple-ramp column-parallel ADC architectures for CMOS image sensors

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Abstract

This paper presents a CMOS imager with a column-parallel ADC architecture based on a multiple-ramp single-slope (MRSS) ADC. Like the well-known column-level single-slope ADC, an MRSS ADC uses a very simple analog column circuit, which mainly consists of an analog comparator and some switches. A prototype imager using the MRSS ADC architecture was realized in a 0.25 $mu{hbox {m}}$ CMOS process. Measurements demonstrate that the conversion speed of an MRSS ADC is 3.3 $times$ higher than a single-slope ADC while dissipating only 16% more power. Furthermore, the MRSS ADC can be easily adapted to exhibit a companding characteristic, which exploits the amplitude-dependent nature of the photon shot noise present in imager signals. Measurements show that the resulting multiple-ramp multiple-slope ADC is 25% faster than an MRSS ADC while dissipating the same amount of power.
Original languageUndefined/Unknown
Pages (from-to)2968-2977
Number of pages10
JournalIEEE Journal of Solid State Circuits
Volume42
Issue number12
DOIs
Publication statusPublished - 2007

Keywords

  • academic journal papers
  • CWTS 0.75 <= JFIS < 2.00

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