Nanometer CMOS characterization and compact modeling at deep-cryogenic temperatures

R.M. Incandela; L.  Song; H.A.R. Homulle; F. Sebastiano; E. Charbon; A. Vladimirescu

doi:10.1109/ESSDERC.2017.8066591

Nanometer CMOS characterization and compact modeling at deep-cryogenic temperatures

R.M. Incandela, L. Song, H.A.R. Homulle, F. Sebastiano, E. Charbon, A. Vladimirescu

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

27 Citations (Scopus)

Abstract

The characterization of nanometer CMOS transistors of different aspect ratios at deep-cryogenic temperatures (4 K and 100 mK) is presented for two standard CMOS technologies (40 nm and 160 nm). A detailed understanding of the device physics at those temperatures was developed and captured in an augmented MOS11/PSP model. The accuracy of the proposed model is demonstrated by matching simulations and measurements for DC and time-domain at 4 K and, for the first time, at 100 mK.

Original language	English
Title of host publication	2017 47th European Solid-State Device Research Conference, ESSDERC 2017
Editors	Jo Boeck, De, Georges Gielen
Publisher	Editions Frontieres
Pages	58-61
Number of pages	4
ISBN (Electronic)	978-150905978-2
DOIs	https://doi.org/10.1109/ESSDERC.2017.8066591
Publication status	Published - 12 Oct 2017
Event	ESSDERC-ESSCIRC 2017: 47th European Solid-State Device Research Conference - 43rd European Solid-State Circuits Conference - Leuven, Belgium Duration: 11 Sept 2017 → 14 Sept 2017 https://www.esscirc-essderc2017.org/

Conference

Conference	ESSDERC-ESSCIRC 2017
Country/Territory	Belgium
City	Leuven
Period	11/09/17 → 14/09/17
Internet address	https://www.esscirc-essderc2017.org/

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10.1109/ESSDERC.2017.8066591

Cite this

Incandela, R. M., Song, L., Homulle, H. A. R., Sebastiano, F., Charbon, E., & Vladimirescu, A. (2017). Nanometer CMOS characterization and compact modeling at deep-cryogenic temperatures. In J. Boeck, De, & G. Gielen (Eds.), 2017 47th European Solid-State Device Research Conference, ESSDERC 2017 (pp. 58-61). Article 8066591 Editions Frontieres. https://doi.org/10.1109/ESSDERC.2017.8066591

@inproceedings{b309596361d6411780a2d1981a7cd138,

title = "Nanometer CMOS characterization and compact modeling at deep-cryogenic temperatures",

abstract = "The characterization of nanometer CMOS transistors of different aspect ratios at deep-cryogenic temperatures (4 K and 100 mK) is presented for two standard CMOS technologies (40 nm and 160 nm). A detailed understanding of the device physics at those temperatures was developed and captured in an augmented MOS11/PSP model. The accuracy of the proposed model is demonstrated by matching simulations and measurements for DC and time-domain at 4 K and, for the first time, at 100 mK.",

author = "R.M. Incandela and L. Song and H.A.R. Homulle and F. Sebastiano and E. Charbon and A. Vladimirescu",

year = "2017",

month = oct,

day = "12",

doi = "10.1109/ESSDERC.2017.8066591",

language = "English",

pages = "58--61",

editor = "{Boeck, De}, Jo and Georges Gielen",

booktitle = "2017 47th European Solid-State Device Research Conference, ESSDERC 2017",

publisher = "Editions Frontieres",

note = "ESSDERC-ESSCIRC 2017 : 47th European Solid-State Device Research Conference - 43rd European Solid-State Circuits Conference ; Conference date: 11-09-2017 Through 14-09-2017",

url = "https://www.esscirc-essderc2017.org/",

}

Incandela, RM, Song, L, Homulle, HAR, Sebastiano, F , Charbon, E & Vladimirescu, A 2017, Nanometer CMOS characterization and compact modeling at deep-cryogenic temperatures. in J Boeck, De & G Gielen (eds), 2017 47th European Solid-State Device Research Conference, ESSDERC 2017., 8066591, Editions Frontieres, pp. 58-61, ESSDERC-ESSCIRC 2017, Leuven, Belgium, 11/09/17. https://doi.org/10.1109/ESSDERC.2017.8066591

Nanometer CMOS characterization and compact modeling at deep-cryogenic temperatures. / Incandela, R.M.; Song, L.; Homulle, H.A.R. et al.
2017 47th European Solid-State Device Research Conference, ESSDERC 2017. ed. / Jo Boeck, De; Georges Gielen. Editions Frontieres, 2017. p. 58-61 8066591.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

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AU - Incandela, R.M.

AU - Song, L.

AU - Homulle, H.A.R.

AU - Sebastiano, F.

AU - Charbon, E.

AU - Vladimirescu, A.

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N2 - The characterization of nanometer CMOS transistors of different aspect ratios at deep-cryogenic temperatures (4 K and 100 mK) is presented for two standard CMOS technologies (40 nm and 160 nm). A detailed understanding of the device physics at those temperatures was developed and captured in an augmented MOS11/PSP model. The accuracy of the proposed model is demonstrated by matching simulations and measurements for DC and time-domain at 4 K and, for the first time, at 100 mK.

AB - The characterization of nanometer CMOS transistors of different aspect ratios at deep-cryogenic temperatures (4 K and 100 mK) is presented for two standard CMOS technologies (40 nm and 160 nm). A detailed understanding of the device physics at those temperatures was developed and captured in an augmented MOS11/PSP model. The accuracy of the proposed model is demonstrated by matching simulations and measurements for DC and time-domain at 4 K and, for the first time, at 100 mK.

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BT - 2017 47th European Solid-State Device Research Conference, ESSDERC 2017

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Y2 - 11 September 2017 through 14 September 2017

ER -

Nanometer CMOS characterization and compact modeling at deep-cryogenic temperatures

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