On-chip output stage design for a continuous class-F power amplifier

Anil Kumar Kumaran; Masoud Pashaeifar; Marco D'Avino; Leo C.N. de Vreede; Morteza S. Alavi

doi:10.1109/ISCAS51556.2021.9401788

On-chip output stage design for a continuous class-F power amplifier

Anil Kumar Kumaran, Masoud Pashaeifar, Marco D'Avino, Leo C.N. de Vreede, Morteza S. Alavi

Electronics

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

3 Citations (Scopus)

112 Downloads (Pure)

Abstract

Continuous Class F (CCF) power amplifiers (PAs) overcome Class-F PA's disadvantage of narrow bandwidth by relaxing the short-circuit requirement at the 2^nd harmonic while still maintaining 90.7% peak efficiency over the band of interest. This paper proposes four different CCF output networks, with their design procedure, suitable for on-chip implementation in the 2.1-2.7GHz band. The output stage with 2^nd harmonic trap and no RF choke is favoured due to its flat real impedance, low fundamental reactance, and compact layout. Using a 40nm CMOS process, a passive efficiency of 68% at 2.4GHz for this structure is in reach.

Original language	English
Title of host publication	2021 IEEE International Symposium on Circuits and Systems (ISCAS)
Place of Publication	Piscataway
Publisher	IEEE
Number of pages	5
ISBN (Electronic)	978-1-7281-9201-7
DOIs	https://doi.org/10.1109/ISCAS51556.2021.9401788
Publication status	Published - 2021
Event	53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Virtual at Daegu, Korea, Republic of Duration: 22 May 2021 → 28 May 2021

Conference

Conference	53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021
Country/Territory	Korea, Republic of
City	Virtual at Daegu
Period	22/05/21 → 28/05/21

Bibliographical note

Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care
Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.

Keywords

Common-mode analysis
Continuous class F (CCF)
Differential-mode analysis
Harmonic termination
Output matching network
Power amplifier (PA)

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10.1109/ISCAS51556.2021.9401788

09401788Final published version, 3.58 MB

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@inproceedings{319781740bf14206a4717432b530aad8,

title = "On-chip output stage design for a continuous class-F power amplifier",

abstract = "Continuous Class F (CCF) power amplifiers (PAs) overcome Class-F PA's disadvantage of narrow bandwidth by relaxing the short-circuit requirement at the 2nd harmonic while still maintaining 90.7% peak efficiency over the band of interest. This paper proposes four different CCF output networks, with their design procedure, suitable for on-chip implementation in the 2.1-2.7GHz band. The output stage with 2nd harmonic trap and no RF choke is favoured due to its flat real impedance, low fundamental reactance, and compact layout. Using a 40nm CMOS process, a passive efficiency of 68% at 2.4GHz for this structure is in reach.",

keywords = "Common-mode analysis, Continuous class F (CCF), Differential-mode analysis, Harmonic termination, Output matching network, Power amplifier (PA)",

author = "Kumaran, {Anil Kumar} and Masoud Pashaeifar and Marco D'Avino and {de Vreede}, {Leo C.N.} and Alavi, {Morteza S.}",

note = "Green Open Access added to TU Delft Institutional Repository {\textquoteleft}You share, we take care!{\textquoteright} – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public. ; 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021 ; Conference date: 22-05-2021 Through 28-05-2021",

year = "2021",

doi = "10.1109/ISCAS51556.2021.9401788",

language = "English",

booktitle = "2021 IEEE International Symposium on Circuits and Systems (ISCAS)",

publisher = "IEEE",

address = "United States",

}

Kumaran, AK , Pashaeifar, M, D'Avino, M, de Vreede, LCN & Alavi, MS 2021, On-chip output stage design for a continuous class-F power amplifier. in 2021 IEEE International Symposium on Circuits and Systems (ISCAS)., 9401788, IEEE, Piscataway, 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021, Virtual at Daegu, Korea, Republic of, 22/05/21. https://doi.org/10.1109/ISCAS51556.2021.9401788

TY - GEN

T1 - On-chip output stage design for a continuous class-F power amplifier

AU - Kumaran, Anil Kumar

AU - Pashaeifar, Masoud

AU - D'Avino, Marco

AU - de Vreede, Leo C.N.

AU - Alavi, Morteza S.

N1 - Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.

PY - 2021

Y1 - 2021

N2 - Continuous Class F (CCF) power amplifiers (PAs) overcome Class-F PA's disadvantage of narrow bandwidth by relaxing the short-circuit requirement at the 2nd harmonic while still maintaining 90.7% peak efficiency over the band of interest. This paper proposes four different CCF output networks, with their design procedure, suitable for on-chip implementation in the 2.1-2.7GHz band. The output stage with 2nd harmonic trap and no RF choke is favoured due to its flat real impedance, low fundamental reactance, and compact layout. Using a 40nm CMOS process, a passive efficiency of 68% at 2.4GHz for this structure is in reach.

AB - Continuous Class F (CCF) power amplifiers (PAs) overcome Class-F PA's disadvantage of narrow bandwidth by relaxing the short-circuit requirement at the 2nd harmonic while still maintaining 90.7% peak efficiency over the band of interest. This paper proposes four different CCF output networks, with their design procedure, suitable for on-chip implementation in the 2.1-2.7GHz band. The output stage with 2nd harmonic trap and no RF choke is favoured due to its flat real impedance, low fundamental reactance, and compact layout. Using a 40nm CMOS process, a passive efficiency of 68% at 2.4GHz for this structure is in reach.

KW - Common-mode analysis

KW - Continuous class F (CCF)

KW - Differential-mode analysis

KW - Harmonic termination

KW - Output matching network

KW - Power amplifier (PA)

UR - http://www.scopus.com/inward/record.url?scp=85109043006&partnerID=8YFLogxK

U2 - 10.1109/ISCAS51556.2021.9401788

DO - 10.1109/ISCAS51556.2021.9401788

M3 - Conference contribution

AN - SCOPUS:85109043006

BT - 2021 IEEE International Symposium on Circuits and Systems (ISCAS)

PB - IEEE

CY - Piscataway

T2 - 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021

Y2 - 22 May 2021 through 28 May 2021

ER -

On-chip output stage design for a continuous class-F power amplifier

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Keywords

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