On-chip output stage design for a continuous class-F power amplifier

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Abstract

Continuous Class F (CCF) power amplifiers (PAs) overcome Class-F PA's disadvantage of narrow bandwidth by relaxing the short-circuit requirement at the 2nd harmonic while still maintaining 90.7% peak efficiency over the band of interest. This paper proposes four different CCF output networks, with their design procedure, suitable for on-chip implementation in the 2.1-2.7GHz band. The output stage with 2nd harmonic trap and no RF choke is favoured due to its flat real impedance, low fundamental reactance, and compact layout. Using a 40nm CMOS process, a passive efficiency of 68% at 2.4GHz for this structure is in reach.

Original languageEnglish
Title of host publication2021 IEEE International Symposium on Circuits and Systems (ISCAS)
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Number of pages5
ISBN (Electronic)978-1-7281-9201-7
DOIs
Publication statusPublished - 2021
Event53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Virtual at Daegu, Korea, Republic of
Duration: 22 May 202128 May 2021

Conference

Conference53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021
Country/TerritoryKorea, Republic of
CityVirtual at Daegu
Period22/05/2128/05/21

Bibliographical note

Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care
Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.

Keywords

  • Common-mode analysis
  • Continuous class F (CCF)
  • Differential-mode analysis
  • Harmonic termination
  • Output matching network
  • Power amplifier (PA)

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