On Structured Design Space Exploration for Mapping of Quantum Algorithms

Medina Bandic, Hossein Zarein, Eduard Alarcon, Carmen G. Almudever

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

1 Citation (Scopus)
30 Downloads (Pure)

Abstract

Quantum algorithms can be expressed as quantum circuits when the circuit model of computation is adopted. Such a circuit description is usually hardware-agnostic, that is, it does not consider the limitations that the quantum hardware might have. In order to make quantum algorithms executable on quantum devices they need to comply to their constraints, which mainly affect the parallelism of quantum operations and the possible interactions between the qubits. The process of adapting a quantum circuit to meet the quantum chip restrictions is known as mapping. The resulting circuit usually has a higher number of gates and depth, decreasing the algorithm's reliability. Different mapping solutions have been already proposed. Most of them are meant for a specific quantum processor and differ in methodology, approach and features. In addition, they are usually only compared in terms of added gates, circuit depth and compilation time. No thorough comparative analysis of the different mapping solutions performance and features has been performed so far.In this paper, we propose to apply structured design space exploration (DSE) methodologies to the mapping procedures. This will allow not only to have a more in depth and structured analysis of their performance but also to identify what features are key and worth to implement. By using DSE we will be able to: i) determine in what regimes some mapping solutions outperform others; ii) derive optimal mapping strategies for specific quantum algorithms and quantum processors; and iii) perform an scalability analysis. In addition, DSE techniques cannot only be applied to the mapping layer that is key for bridging quantum applications to quantum devices, but also to the full-stack quantum computing system allowing for its crosslayer co-design.

Original languageEnglish
Title of host publication2020 35th Conference on Design of Circuits and Integrated Systems, DCIS 2020
EditorsM. Lopez-Vallejo, C. López Barrio
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Number of pages6
ISBN (Electronic)9781728191324
DOIs
Publication statusPublished - 2020
Event35th Conference on Design of Circuits and Integrated Systems, DCIS 2020 - Segovia, Spain
Duration: 18 Nov 202020 Nov 2020

Publication series

Name2020 35th Conference on Design of Circuits and Integrated Systems, DCIS 2020

Conference

Conference35th Conference on Design of Circuits and Integrated Systems, DCIS 2020
CountrySpain
CitySegovia
Period18/11/2020/11/20

Keywords

  • Design Space Exploration
  • quantum benchmarks
  • Quantum circuit mapping
  • quantum performance metrics

Fingerprint

Dive into the research topics of 'On Structured Design Space Exploration for Mapping of Quantum Algorithms'. Together they form a unique fingerprint.

Cite this