TY - GEN
T1 - On Structured Design Space Exploration for Mapping of Quantum Algorithms
AU - Bandic, Medina
AU - Zarein, Hossein
AU - Alarcon, Eduard
AU - Almudever, Carmen G.
PY - 2020
Y1 - 2020
N2 - Quantum algorithms can be expressed as quantum circuits when the circuit model of computation is adopted. Such a circuit description is usually hardware-agnostic, that is, it does not consider the limitations that the quantum hardware might have. In order to make quantum algorithms executable on quantum devices they need to comply to their constraints, which mainly affect the parallelism of quantum operations and the possible interactions between the qubits. The process of adapting a quantum circuit to meet the quantum chip restrictions is known as mapping. The resulting circuit usually has a higher number of gates and depth, decreasing the algorithm's reliability. Different mapping solutions have been already proposed. Most of them are meant for a specific quantum processor and differ in methodology, approach and features. In addition, they are usually only compared in terms of added gates, circuit depth and compilation time. No thorough comparative analysis of the different mapping solutions performance and features has been performed so far.In this paper, we propose to apply structured design space exploration (DSE) methodologies to the mapping procedures. This will allow not only to have a more in depth and structured analysis of their performance but also to identify what features are key and worth to implement. By using DSE we will be able to: i) determine in what regimes some mapping solutions outperform others; ii) derive optimal mapping strategies for specific quantum algorithms and quantum processors; and iii) perform an scalability analysis. In addition, DSE techniques cannot only be applied to the mapping layer that is key for bridging quantum applications to quantum devices, but also to the full-stack quantum computing system allowing for its crosslayer co-design.
AB - Quantum algorithms can be expressed as quantum circuits when the circuit model of computation is adopted. Such a circuit description is usually hardware-agnostic, that is, it does not consider the limitations that the quantum hardware might have. In order to make quantum algorithms executable on quantum devices they need to comply to their constraints, which mainly affect the parallelism of quantum operations and the possible interactions between the qubits. The process of adapting a quantum circuit to meet the quantum chip restrictions is known as mapping. The resulting circuit usually has a higher number of gates and depth, decreasing the algorithm's reliability. Different mapping solutions have been already proposed. Most of them are meant for a specific quantum processor and differ in methodology, approach and features. In addition, they are usually only compared in terms of added gates, circuit depth and compilation time. No thorough comparative analysis of the different mapping solutions performance and features has been performed so far.In this paper, we propose to apply structured design space exploration (DSE) methodologies to the mapping procedures. This will allow not only to have a more in depth and structured analysis of their performance but also to identify what features are key and worth to implement. By using DSE we will be able to: i) determine in what regimes some mapping solutions outperform others; ii) derive optimal mapping strategies for specific quantum algorithms and quantum processors; and iii) perform an scalability analysis. In addition, DSE techniques cannot only be applied to the mapping layer that is key for bridging quantum applications to quantum devices, but also to the full-stack quantum computing system allowing for its crosslayer co-design.
KW - Design Space Exploration
KW - quantum benchmarks
KW - Quantum circuit mapping
KW - quantum performance metrics
UR - http://www.scopus.com/inward/record.url?scp=85098663710&partnerID=8YFLogxK
U2 - 10.1109/DCIS51330.2020.9268670
DO - 10.1109/DCIS51330.2020.9268670
M3 - Conference contribution
AN - SCOPUS:85098663710
T3 - 2020 35th Conference on Design of Circuits and Integrated Systems, DCIS 2020
BT - 2020 35th Conference on Design of Circuits and Integrated Systems, DCIS 2020
A2 - Lopez-Vallejo, M.
A2 - López Barrio, C.
PB - Institute of Electrical and Electronics Engineers (IEEE)
T2 - 35th Conference on Design of Circuits and Integrated Systems, DCIS 2020
Y2 - 18 November 2020 through 20 November 2020
ER -