Open-source IP cores for space: A processor-level perspective on soft errors in the RISC-V era

Stefano Di Mascio*, Alessandra Menicucci, Eberhard Gill, Gianluca Furano, Claudio Monteleone

*Corresponding author for this work

Research output: Contribution to journalReview articlepeer-review

5 Citations (Scopus)
298 Downloads (Pure)


This paper discusses principles and techniques to evaluate processors for dependable computing in space applications. The focus is on soft errors, which dominate the failure rate of processors in space. Error, failure and propagation models from literature are selected and employed to estimate the failure rate due to soft errors in typical processor designs. A similar approach can be followed for applications with different radiation environments (e.g. automotive, servers, experimental instrumentation exposed to radiation on ground), by adapting the error models. This detailed white-box analysis is possible only for open-source Intellectual Property (IP) cores and in this work it will be applied to several open-source IP cores based on the RISC-V Instruction Set Architecture (ISA). For these case studies, several types of redundancy described in literature for space processors will be evaluated in terms of their cost-effectiveness and expected final in-orbit behavior. This work provides a comprehensive framework to assess efficacy and cost-effectiveness of redundancy, instead of listing and categorizing the techniques described in literature without assessing their relevance to state-of-the-art designs in space applications.

Original languageEnglish
Article number100349
Number of pages25
JournalComputer Science Review
Publication statusPublished - 2021


  • Fault tolerance
  • Processors
  • Space


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