P-GaAs Nanowire Metal-Semiconductor Field-Effect Transistors with Near-Thermal Limit Gating

A. R. Ullah, F. Meyer, J. G. Gluschke, S. Naureen, P. Caroff, P. Krogstrup, J. Nygård, A. P. Micolich*

*Corresponding author for this work

Research output: Contribution to journalArticleScientificpeer-review

6 Citations (Scopus)


Difficulties in obtaining high-performance p-type transistors and gate insulator charge-trapping effects present two major challenges for III-V complementary metal-oxide semiconductor (CMOS) electronics. We report a p-GaAs nanowire metal-semiconductor field-effect transistor (MESFET) that eliminates the need for a gate insulator by exploiting the Schottky barrier at the metal-GaAs interface. Our device beats the best-performing p-GaSb nanowire metal-oxide-semiconductor field effect transistor (MOSFET), giving a typical subthreshold swing of 62 mV/dec, within 4% of the thermal limit, on-off ratio ∼105, on-resistance ∼700 kω, contact resistance ∼30 kω, peak transconductance 1.2 μS/μm, and high-fidelity ac operation at frequencies up to 10 kHz. The device consists of a GaAs nanowire with an undoped core and heavily Be-doped shell. We carefully etch back the nanowire at the gate locations to obtain Schottky-barrier insulated gates while leaving the doped shell intact at the contacts to obtain low contact resistance. Our device opens a path to all-GaAs nanowire MESFET complementary circuits with simplified fabrication and improved performance.

Original languageEnglish
Pages (from-to)5673-5680
JournalNano Letters
Issue number9
Publication statusPublished - 2018


  • Nanowire
  • p-GaAs
  • Schottky gate
  • transistor


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