Package-Level Electro-Thermal Simulation with Transient Thermal Resistance Model for Surge Stress Failure Analysis of SiC MOSFET

This paper investigates the surge reliability of commercial 1200V SiC MOSFETs through a combined approach of experimental testing and multiphysics simulation, elucidating the failure mechanisms under both step and repetitive surge current stress. The innovative integration of package-level electro-thermal coupling simulation with transient junction temperature estimation overcomes the limitations of conventional methodologies that rely solely on decapsulation analysis and Technology Computer Aided Design (TCAD) simulation. Experimental evaluations on six Devices Under Test (DUTs) with distinct structural configurations, employing surge testing and failure analysis techniques including C-mode Scanning Acoustic Microscopy (C-SAM), optical microscopy, and Scanning Electron Microscope (SEM), confirm that device failure primarily originates from gate-source short circuits caused by aluminum bonding wire melting. COMSOL multiphysics simulations further replicate the transient thermal characteristics of bonding wire regions, demonstrating rapid temperature escalation to the Aluminum melting point within 5-6 ms during surge events. A transient thermal resistance-based junction temperature characterization method is proposed, revealing an inverse proportionality between thermal resistance and chip area.