Performance Enhancement with a Capacitor-Scaling Design for SSHC Piezoelectric Energy Harvesting Interfaces

Yiwei  Zou; Sijun  Du

doi:10.1109/ISCAS48785.2022.9937764

Performance Enhancement with a Capacitor-Scaling Design for SSHC Piezoelectric Energy Harvesting Interfaces

Yiwei Zou, Sijun Du^*

^*Corresponding author for this work

Electronic Instrumentation

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

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Abstract

Piezoelectric energy harvesting (PEH) has attracted much attention as an approach to exploit ambient vibrational energy to power self-sustained devices. Among the proposed interface circuits for PEH, Synchronized Switch Harvesting on Capacitor (SSHC) rectifier distinguishes itself since it achieves high power efficiency while requires no inductor. The power SSHC can extract is a function of the voltage flip efficiency. In previous studies the flip efficiency is given only under particular condition, which limits the analysis and design of SSHC circuits. This paper presents the derivation of a generic flip efficiency expression. From the result, a novel capacitor-scaling design is proposed which can reduce the total switched capacitance by up to 50% while achieving the same performance (or to enhance performance while maintaining the total capacitance). This is particularly preferred for a fully integrated design and can validated by simulations implemented in a 0.18 m. CMOS BCD technology.

Original language	English
Title of host publication	Proceedings of the 2022 IEEE International Symposium on Circuits and Systems (ISCAS)
Place of Publication	Danvers
Publisher	IEEE
Pages	2758-2762
Number of pages	5
ISBN (Electronic)	978-1-6654-8485-5
ISBN (Print)	978-1-6654-8486-2
DOIs	https://doi.org/10.1109/ISCAS48785.2022.9937764
Publication status	Published - 2022
Event	2022 IEEE International Symposium on Circuits and Systems (ISCAS) - Austin, United States Duration: 27 May 2022 → 1 Jun 2022

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2022-May
ISSN (Print)	0271-4310

Conference

Conference	2022 IEEE International Symposium on Circuits and Systems (ISCAS)
Country/Territory	United States
City	Austin
Period	27/05/22 → 1/06/22

Bibliographical note

Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care

Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.

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Zou, Y., & Du, S. (2022). Performance Enhancement with a Capacitor-Scaling Design for SSHC Piezoelectric Energy Harvesting Interfaces. In Proceedings of the 2022 IEEE International Symposium on Circuits and Systems (ISCAS) (pp. 2758-2762). (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2022-May). IEEE. https://doi.org/10.1109/ISCAS48785.2022.9937764

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title = "Performance Enhancement with a Capacitor-Scaling Design for SSHC Piezoelectric Energy Harvesting Interfaces",

abstract = "Piezoelectric energy harvesting (PEH) has attracted much attention as an approach to exploit ambient vibrational energy to power self-sustained devices. Among the proposed interface circuits for PEH, Synchronized Switch Harvesting on Capacitor (SSHC) rectifier distinguishes itself since it achieves high power efficiency while requires no inductor. The power SSHC can extract is a function of the voltage flip efficiency. In previous studies the flip efficiency is given only under particular condition, which limits the analysis and design of SSHC circuits. This paper presents the derivation of a generic flip efficiency expression. From the result, a novel capacitor-scaling design is proposed which can reduce the total switched capacitance by up to 50\% while achieving the same performance (or to enhance performance while maintaining the total capacitance). This is particularly preferred for a fully integrated design and can validated by simulations implemented in a 0.18 m. CMOS BCD technology.",

author = "Yiwei Zou and Sijun Du",

note = "Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.; 2022 IEEE International Symposium on Circuits and Systems (ISCAS) ; Conference date: 27-05-2022 Through 01-06-2022",

year = "2022",

doi = "10.1109/ISCAS48785.2022.9937764",

language = "English",

isbn = "978-1-6654-8486-2",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "IEEE",

pages = "2758--2762",

booktitle = "Proceedings of the 2022 IEEE International Symposium on Circuits and Systems (ISCAS)",

address = "United States",

}

Zou, Y & Du, S 2022, Performance Enhancement with a Capacitor-Scaling Design for SSHC Piezoelectric Energy Harvesting Interfaces. in Proceedings of the 2022 IEEE International Symposium on Circuits and Systems (ISCAS). Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2022-May, IEEE, Danvers, pp. 2758-2762, 2022 IEEE International Symposium on Circuits and Systems (ISCAS), Austin, United States, 27/05/22. https://doi.org/10.1109/ISCAS48785.2022.9937764

Performance Enhancement with a Capacitor-Scaling Design for SSHC Piezoelectric Energy Harvesting Interfaces. / Zou, Yiwei; Du, Sijun .
Proceedings of the 2022 IEEE International Symposium on Circuits and Systems (ISCAS). Danvers: IEEE, 2022. p. 2758-2762 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2022-May).

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

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AU - Zou, Yiwei

AU - Du, Sijun

N1 - Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.

PY - 2022

Y1 - 2022

N2 - Piezoelectric energy harvesting (PEH) has attracted much attention as an approach to exploit ambient vibrational energy to power self-sustained devices. Among the proposed interface circuits for PEH, Synchronized Switch Harvesting on Capacitor (SSHC) rectifier distinguishes itself since it achieves high power efficiency while requires no inductor. The power SSHC can extract is a function of the voltage flip efficiency. In previous studies the flip efficiency is given only under particular condition, which limits the analysis and design of SSHC circuits. This paper presents the derivation of a generic flip efficiency expression. From the result, a novel capacitor-scaling design is proposed which can reduce the total switched capacitance by up to 50% while achieving the same performance (or to enhance performance while maintaining the total capacitance). This is particularly preferred for a fully integrated design and can validated by simulations implemented in a 0.18 m. CMOS BCD technology.

AB - Piezoelectric energy harvesting (PEH) has attracted much attention as an approach to exploit ambient vibrational energy to power self-sustained devices. Among the proposed interface circuits for PEH, Synchronized Switch Harvesting on Capacitor (SSHC) rectifier distinguishes itself since it achieves high power efficiency while requires no inductor. The power SSHC can extract is a function of the voltage flip efficiency. In previous studies the flip efficiency is given only under particular condition, which limits the analysis and design of SSHC circuits. This paper presents the derivation of a generic flip efficiency expression. From the result, a novel capacitor-scaling design is proposed which can reduce the total switched capacitance by up to 50% while achieving the same performance (or to enhance performance while maintaining the total capacitance). This is particularly preferred for a fully integrated design and can validated by simulations implemented in a 0.18 m. CMOS BCD technology.

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SN - 978-1-6654-8486-2

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BT - Proceedings of the 2022 IEEE International Symposium on Circuits and Systems (ISCAS)

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Performance Enhancement with a Capacitor-Scaling Design for SSHC Piezoelectric Energy Harvesting Interfaces

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