Pinhole Defect Characterization and Fault Modeling for STT-MRAM Testing

Lizhou Wu; Siddharth Rao; Guilherme Cardoso Medeiros; Mottaqiallah Taouil; Erik Jan Marinissen; Farrukh Yasin; Sebastien Couet; Said Hamdioui; Gouri Sankar Kar

doi:10.1109/ETS.2019.8791518

Pinhole Defect Characterization and Fault Modeling for STT-MRAM Testing

Lizhou Wu, Siddharth Rao, Guilherme Cardoso Medeiros, Mottaqiallah Taouil, Erik Jan Marinissen, Farrukh Yasin, Sebastien Couet, Said Hamdioui, Gouri Sankar Kar

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

15 Citations (Scopus)

Abstract

The STT-MRAM manufacturing process involves not only traditional CMOS process steps, but also the integration of magnetic tunnel junction (MTJ) devices, the data-storing elements. This paper demonstrates a paradigm shift in fault modeling for STT-MRAMs by performing defect modeling and fault analysis for MTJ pinhole defects which are seen as a key type of STT-MRAM manufacturing defects. A Verilog-A compact model for defect-free MTJ devices is built and calibrated with electrical measurements on actual MTJ wafers. MTJs with a pinhole defect are extensively characterized, both during manufacturing test (t=0) and in the field (t>0), and the data is used to extend our defect-free MTJ compact model to include parameterized pinhole defects. The model is then used to perform single-cell static fault analysis and this shows not only what kind of faults can occur in an STT-MRAM, but also that the conventional fault modeling approach based on linear resistors cannot catch such behavior.

Original language	English
Title of host publication	2019 IEEE European Test Symposium (ETS)
Subtitle of host publication	Proceedings
Place of Publication	Danvers
Publisher	IEEE
Pages	1-6
Number of pages	6
ISBN (Electronic)	978-1-7281-1173-5
ISBN (Print)	978-1-7281-1174-2
DOIs	https://doi.org/10.1109/ETS.2019.8791518
Publication status	Published - 2019
Event	24th IEEE European Test Symposium 2019 - Baden-Baden, Germany Duration: 27 May 2019 → 31 May 2019 Conference number: 24th http://www.testgroup.polito.it/ets19

Conference

Conference	24th IEEE European Test Symposium 2019
Abbreviated title	ETS
Country/Territory	Germany
City	Baden-Baden
Period	27/05/19 → 31/05/19
Internet address	http://www.testgroup.polito.it/ets19

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@inproceedings{d2f0cce13f114d25ab74f73e4f60c551,

title = "Pinhole Defect Characterization and Fault Modeling for STT-MRAM Testing",

abstract = "The STT-MRAM manufacturing process involves not only traditional CMOS process steps, but also the integration of magnetic tunnel junction (MTJ) devices, the data-storing elements. This paper demonstrates a paradigm shift in fault modeling for STT-MRAMs by performing defect modeling and fault analysis for MTJ pinhole defects which are seen as a key type of STT-MRAM manufacturing defects. A Verilog-A compact model for defect-free MTJ devices is built and calibrated with electrical measurements on actual MTJ wafers. MTJs with a pinhole defect are extensively characterized, both during manufacturing test (t=0) and in the field (t>0), and the data is used to extend our defect-free MTJ compact model to include parameterized pinhole defects. The model is then used to perform single-cell static fault analysis and this shows not only what kind of faults can occur in an STT-MRAM, but also that the conventional fault modeling approach based on linear resistors cannot catch such behavior.",

author = "Lizhou Wu and Siddharth Rao and {Cardoso Medeiros}, Guilherme and Mottaqiallah Taouil and Marinissen, {Erik Jan} and Farrukh Yasin and Sebastien Couet and Said Hamdioui and Kar, {Gouri Sankar}",

year = "2019",

doi = "10.1109/ETS.2019.8791518",

language = "English",

isbn = " 978-1-7281-1174-2",

pages = "1--6",

booktitle = "2019 IEEE European Test Symposium (ETS)",

publisher = "IEEE",

address = "United States",

note = "24th IEEE European Test Symposium 2019, ETS ; Conference date: 27-05-2019 Through 31-05-2019",

url = "http://www.testgroup.polito.it/ets19",

}

Wu, L, Rao, S, Cardoso Medeiros, G, Taouil, M, Marinissen, EJ, Yasin, F, Couet, S, Hamdioui, S & Kar, GS 2019, Pinhole Defect Characterization and Fault Modeling for STT-MRAM Testing. in 2019 IEEE European Test Symposium (ETS): Proceedings., 8791518, IEEE, Danvers, pp. 1-6, 24th IEEE European Test Symposium 2019, Baden-Baden, Germany, 27/05/19. https://doi.org/10.1109/ETS.2019.8791518

TY - GEN

T1 - Pinhole Defect Characterization and Fault Modeling for STT-MRAM Testing

AU - Wu, Lizhou

AU - Rao, Siddharth

AU - Cardoso Medeiros, Guilherme

AU - Taouil, Mottaqiallah

AU - Marinissen, Erik Jan

AU - Yasin, Farrukh

AU - Couet, Sebastien

AU - Hamdioui, Said

AU - Kar, Gouri Sankar

N1 - Conference code: 24th

PY - 2019

Y1 - 2019

N2 - The STT-MRAM manufacturing process involves not only traditional CMOS process steps, but also the integration of magnetic tunnel junction (MTJ) devices, the data-storing elements. This paper demonstrates a paradigm shift in fault modeling for STT-MRAMs by performing defect modeling and fault analysis for MTJ pinhole defects which are seen as a key type of STT-MRAM manufacturing defects. A Verilog-A compact model for defect-free MTJ devices is built and calibrated with electrical measurements on actual MTJ wafers. MTJs with a pinhole defect are extensively characterized, both during manufacturing test (t=0) and in the field (t>0), and the data is used to extend our defect-free MTJ compact model to include parameterized pinhole defects. The model is then used to perform single-cell static fault analysis and this shows not only what kind of faults can occur in an STT-MRAM, but also that the conventional fault modeling approach based on linear resistors cannot catch such behavior.

AB - The STT-MRAM manufacturing process involves not only traditional CMOS process steps, but also the integration of magnetic tunnel junction (MTJ) devices, the data-storing elements. This paper demonstrates a paradigm shift in fault modeling for STT-MRAMs by performing defect modeling and fault analysis for MTJ pinhole defects which are seen as a key type of STT-MRAM manufacturing defects. A Verilog-A compact model for defect-free MTJ devices is built and calibrated with electrical measurements on actual MTJ wafers. MTJs with a pinhole defect are extensively characterized, both during manufacturing test (t=0) and in the field (t>0), and the data is used to extend our defect-free MTJ compact model to include parameterized pinhole defects. The model is then used to perform single-cell static fault analysis and this shows not only what kind of faults can occur in an STT-MRAM, but also that the conventional fault modeling approach based on linear resistors cannot catch such behavior.

UR - http://www.scopus.com/inward/record.url?scp=85071167895&partnerID=8YFLogxK

U2 - 10.1109/ETS.2019.8791518

DO - 10.1109/ETS.2019.8791518

M3 - Conference contribution

SN - 978-1-7281-1174-2

SP - 1

EP - 6

BT - 2019 IEEE European Test Symposium (ETS)

PB - IEEE

CY - Danvers

T2 - 24th IEEE European Test Symposium 2019

Y2 - 27 May 2019 through 31 May 2019

ER -

Pinhole Defect Characterization and Fault Modeling for STT-MRAM Testing

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