Power and Area Efficient Column-Parallel ADC Architectures for CMOS Image Sensors

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

9 Citations (Scopus)

Abstract

The ever-increasing resolution of CMOS imagers has had a profound impact on their analog readout electronics, and, in particular, on their ADC architecture. This paper gives an overview of the development of column-parallel ADCs that enable the high-speed and power-efficient readout of high-resolution CMOS imagers. In particular, the recently proposed multiple-ramp single-slope (MRSS) ADC will be discussed.
Original languageUndefined/Unknown
Title of host publicationProceedings IEEE Sensors 2007
Editors s.n.
Place of PublicationAtlanta
PublisherIEEE Society
Pages523-526
Number of pages4
ISBN (Print)978-1-4244-1262-4
DOIs
Publication statusPublished - 2007
EventIEEE Sensors 2007: 6th IEEE Conference on Sensors - Atlanta, GA, United States
Duration: 28 Oct 200731 Oct 2007

Conference

ConferenceIEEE Sensors 2007
CountryUnited States
CityAtlanta, GA
Period28/10/0731/10/07

Keywords

  • academic journal papers
  • Conf.proc. > 3 pag

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