Power-Efficiency Analysis of Accelerated BWA-MEM Implementations on Heterogeneous Computing Platforms

Ernst Joachim Houtgast, Vlad-Mihai Sima, Giacomo Marchiori, Koen Bertels, Zaid Al-Ars

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

9 Citations (Scopus)
114 Downloads (Pure)


Next Generation Sequencing techniques have dramatically reduced the cost of sequencing genetic material, resulting in huge amounts of data being sequenced. The processing of this data poses huge challenges, both from a performance perspective, as well as from a power-efficiency perspective. Heterogeneous computing can help on both fronts, by enabling more performant and more power-efficient solutions. In this paper, power-efficiency of the BWA-MEM algorithm, a popular tool for genomic data mapping, is studied on two heterogeneous architectures. The performance and power-efficiency of an FPGA-based implementation using a single Xilinx Virtex-7 FPGA on the Alpha Data add-in card is compared to a GPU-based implementation using an NVIDIA GeForce GTX 970 and against the software-only baseline system. By offloading the Seed Extension phase on an accelerator, both implementations are able to achieve a two-fold speedup in overall application-level performance over the software-only implementation. Moreover, the highly customizable nature of the FPGA results in much higher power-efficiency, as the FPGA power consumption is less than one fourth of that of the GPU. To facilitate platform and tool-agnostic comparisons, the base pairs per Joule unit is introduced as a measure of power-efficiency. The FPGA design is able to map up to 44 thousand base pairs per Joule, a 2.1x gain in power-efficiency as compared to the software-only baseline.
Original languageEnglish
Title of host publication2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig)
EditorsPeter Athanas, René Cumplido, Claudia Feregrino, Ron Sass
Place of PublicationDanvers, MA
Number of pages8
ISBN (Electronic)978-1-5090-3707-0
Publication statusPublished - Dec 2016
EventInternational Conference on ReConFigurable Computing and FPGAs, ReConFig 2016 - Cancun, Mexico
Duration: 30 Nov 20162 Dec 2016


ConferenceInternational Conference on ReConFigurable Computing and FPGAs, ReConFig 2016

Bibliographical note

Accepted Author Manuscript


  • read mapping
  • FPGA
  • GPU
  • Next Generation Sequencing
  • power-efficiency


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