TY - GEN
T1 - Pre-Synthesis Evaluation of Digital Bus Micro-Architectures
AU - Garcia-Ramirez, R.
AU - Chacon-Rodriguez, A.
AU - Strydis, C.
AU - Rimolo-Donadio, R.
PY - 2020/2
Y1 - 2020/2
N2 - Buses are central building blocks in the architecture of digital systems. There are numerous standards for bus architectures and evaluation metrics in terms of data transfer rate, quality of service, and latency; however, it is not common to find metrics related to the physical features of bus implementations, such as power consumption and area in terms of their microarchitecture. This paper evaluate bus micro-architectures at pre-synthesis level, allowing for the comparison of alternative circuits implementing the same standard and thus providing estimations on the power consumption and area requirements. A metric is proposed to evaluate the bus implementation and its utilization is shown with generic serial and parallel buses, based on simulations with a 0.18μm CMOS standard cell library.
AB - Buses are central building blocks in the architecture of digital systems. There are numerous standards for bus architectures and evaluation metrics in terms of data transfer rate, quality of service, and latency; however, it is not common to find metrics related to the physical features of bus implementations, such as power consumption and area in terms of their microarchitecture. This paper evaluate bus micro-architectures at pre-synthesis level, allowing for the comparison of alternative circuits implementing the same standard and thus providing estimations on the power consumption and area requirements. A metric is proposed to evaluate the bus implementation and its utilization is shown with generic serial and parallel buses, based on simulations with a 0.18μm CMOS standard cell library.
KW - Bus
KW - Interconnects
KW - Micro-Architecture
KW - System-on-Chip
KW - Very Large Scale Integration
UR - http://www.scopus.com/inward/record.url?scp=85084086762&partnerID=8YFLogxK
U2 - 10.1109/PRIME-LA47693.2020.9062719
DO - 10.1109/PRIME-LA47693.2020.9062719
M3 - Conference contribution
AN - SCOPUS:85084086762
T3 - PRIME-LA 2020 - 3rd IEEE Conference on Ph.D. Research in Microelectronics and Electronics in Latin America, Proceedings
BT - PRIME-LA 2020 - 3rd IEEE Conference on Ph.D. Research in Microelectronics and Electronics in Latin America, Proceedings
PB - IEEE
T2 - 3rd IEEE Conference on Ph.D. Research in Microelectronics and Electronics in Latin America, PRIME-LA 2020
Y2 - 25 February 2020 through 28 February 2020
ER -