Preventing Soft Errors and Hardware Trojans in RISC-V Cores

Edian B. Annink, Gerard Rauwerda, Edwin Hakkennes, Alessandra Menicucci, Stefano Di Mascio, Gianluca Furano, Marco Ottavi

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

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Abstract

Soft errors in embedded systems' memories like single-event upsets and multiple-bit upsets lead to data and instruction corruption. Therefore, devices deployed in harsh environments, such as space, use fault-tolerant processors or redundancy methods to ensure critical application dependability. Another rising concern in secure, critical space applications is the possible introduction of hardware Trojans in an untrusted phase of the manufacturing process. Besides environmental side-effects, an adversary that has injected a malicious mechanism e.g., in the processor or memory can trigger unwanted behavior or leak sensitive information. Techniques to prevent or mitigate hardware Trojans are important to ensure hardware security. Leveraging the openness of the RISC-V ISA, this paper introduces a novel solution to improve the security and dependability of softcores with a low area and latency overhead. The instruction validator which is the first part of this solution can effectively detect hardware Trojans and multiple-bit upsets in the instruction memory by checking instruction/address pairs using a Bloom filter probabilistic data structure. The second part of the solution is the proposal of an error correction code instruction memory using Hamming single-error correction to detect and correct single-event upsets. It has also been proven that the Hamming decoder improves the detection performance of the instruction validator.

Original languageEnglish
Title of host publicationProceedings - 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022
EditorsLuca Cassano, Sreejit Chakravarty, Alberto Bosio
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Number of pages7
ISBN (Electronic)9781665459389
DOIs
Publication statusPublished - 2022
Event35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022 - Austin, United States
Duration: 19 Oct 202221 Oct 2022

Publication series

NameProceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT
Volume2022-October
ISSN (Print)2576-1501
ISSN (Electronic)2765-933X

Conference

Conference35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022
Country/TerritoryUnited States
CityAustin
Period19/10/2221/10/22

Bibliographical note

Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care
Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.

Keywords

  • Bloom Filters
  • Hardware Dependability
  • Hardware Security
  • Hardware Trojans
  • RISC-V

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