PVT Analysis for RRAM and STT-MRAM-based Logic Computation-in-Memory

Moritz Fieback, Christopher Münch, Anteneh Gebregiorgis, Guilherme Cardoso Medeiros, Mottaqiallah Taouil, Said Hamdioui, Mehdi Tahoori

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

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Abstract

Emerging non-volatile resistive memories like Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) and Resistive RAM (RRAM) are in the focus of today’s research. They offer promising alternative computing architectures such as computation-in-memory (CiM) to reduce the transfer overhead between CPU and memory, usually referred to as the memory wall, which is present in all von Neumann architectures. A multitude of architectures with CiM capabilities are based on these devices, due to their inherent resistive behavior and thus their ability to perform calculation directly within the memory, and thus without invoking the CPU at all. However, emerging memories are sensitive to Process, Voltage and Temperature (PVT) variations. This sensitivity has an even larger impact on CiM architectures. In this paper, we analyze and compare the impact of PVT variations on STT-MRAM and RRAM-based CiM architectures. We perform a sensitivity analysis to identify which parts of the CiM structure are most susceptible to PVT variations, for each technology. Based on these analyses, we recommend that STT-MRAM is used in high-performance CiM, while RRAM is used for edge CiM.
Original languageEnglish
Title of host publicationProceedings of the 2022 IEEE European Test Symposium (ETS)
Place of PublicationDanvers
PublisherIEEE
Pages1-6
Number of pages6
ISBN (Electronic)978-1-6654-6706-3
ISBN (Print)978-1-6654-6707-0
DOIs
Publication statusPublished - 2022
Event2022 IEEE European Test Symposium (ETS) - Barcelona, Spain
Duration: 23 May 202227 May 2022

Conference

Conference2022 IEEE European Test Symposium (ETS)
Country/TerritorySpain
CityBarcelona
Period23/05/2227/05/22

Bibliographical note

Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care
Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.

Keywords

  • Computation-in-Memory (CiM)
  • PVT
  • emerging memories
  • STT-MRAM
  • RRAM
  • reliability

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