PVT Analysis for RRAM and STT-MRAM-based Logic Computation-in-Memory

Moritz Fieback; Christopher Münch; Anteneh Gebregiorgis; Guilherme Cardoso Medeiros; Mottaqiallah Taouil; Said Hamdioui; Mehdi Tahoori

doi:10.1109/ETS54262.2022.9810436

PVT Analysis for RRAM and STT-MRAM-based Logic Computation-in-Memory

Moritz Fieback, Christopher Münch, Anteneh Gebregiorgis, Guilherme Cardoso Medeiros, Mottaqiallah Taouil, Said Hamdioui, Mehdi Tahoori

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

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Abstract

Emerging non-volatile resistive memories like Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) and Resistive RAM (RRAM) are in the focus of today’s research. They offer promising alternative computing architectures such as computation-in-memory (CiM) to reduce the transfer overhead between CPU and memory, usually referred to as the memory wall, which is present in all von Neumann architectures. A multitude of architectures with CiM capabilities are based on these devices, due to their inherent resistive behavior and thus their ability to perform calculation directly within the memory, and thus without invoking the CPU at all. However, emerging memories are sensitive to Process, Voltage and Temperature (PVT) variations. This sensitivity has an even larger impact on CiM architectures. In this paper, we analyze and compare the impact of PVT variations on STT-MRAM and RRAM-based CiM architectures. We perform a sensitivity analysis to identify which parts of the CiM structure are most susceptible to PVT variations, for each technology. Based on these analyses, we recommend that STT-MRAM is used in high-performance CiM, while RRAM is used for edge CiM.

Original language	English
Title of host publication	Proceedings of the 2022 IEEE European Test Symposium (ETS)
Place of Publication	Danvers
Publisher	IEEE
Pages	1-6
Number of pages	6
ISBN (Electronic)	978-1-6654-6706-3
ISBN (Print)	978-1-6654-6707-0
DOIs	https://doi.org/10.1109/ETS54262.2022.9810436
Publication status	Published - 2022
Event	2022 IEEE European Test Symposium (ETS) - Barcelona, Spain Duration: 23 May 2022 → 27 May 2022

Conference

Conference	2022 IEEE European Test Symposium (ETS)
Country/Territory	Spain
City	Barcelona
Period	23/05/22 → 27/05/22

Bibliographical note

Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care
Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.

Keywords

Computation-in-Memory (CiM)
PVT
emerging memories
STT-MRAM
RRAM
reliability

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10.1109/ETS54262.2022.9810436

PVT_Analysis_for_RRAM_and_STT_MRAM_based_Logic_Computation_in_MemoryFinal published version, 1.25 MB

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@inproceedings{20549d20628c45e6a78161a876b955b4,

title = "PVT Analysis for RRAM and STT-MRAM-based Logic Computation-in-Memory",

abstract = "Emerging non-volatile resistive memories like Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) and Resistive RAM (RRAM) are in the focus of today{\textquoteright}s research. They offer promising alternative computing architectures such as computation-in-memory (CiM) to reduce the transfer overhead between CPU and memory, usually referred to as the memory wall, which is present in all von Neumann architectures. A multitude of architectures with CiM capabilities are based on these devices, due to their inherent resistive behavior and thus their ability to perform calculation directly within the memory, and thus without invoking the CPU at all. However, emerging memories are sensitive to Process, Voltage and Temperature (PVT) variations. This sensitivity has an even larger impact on CiM architectures. In this paper, we analyze and compare the impact of PVT variations on STT-MRAM and RRAM-based CiM architectures. We perform a sensitivity analysis to identify which parts of the CiM structure are most susceptible to PVT variations, for each technology. Based on these analyses, we recommend that STT-MRAM is used in high-performance CiM, while RRAM is used for edge CiM.",

keywords = "Computation-in-Memory (CiM), PVT, emerging memories, STT-MRAM, RRAM, reliability",

author = "Moritz Fieback and Christopher M{\"u}nch and Anteneh Gebregiorgis and {Cardoso Medeiros}, Guilherme and Mottaqiallah Taouil and Said Hamdioui and Mehdi Tahoori",

note = "Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.; 2022 IEEE European Test Symposium (ETS) ; Conference date: 23-05-2022 Through 27-05-2022",

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doi = "10.1109/ETS54262.2022.9810436",

language = "English",

isbn = "978-1-6654-6707-0",

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Fieback, M, Münch, C, Gebregiorgis, A, Cardoso Medeiros, G, Taouil, M , Hamdioui, S & Tahoori, M 2022, PVT Analysis for RRAM and STT-MRAM-based Logic Computation-in-Memory. in Proceedings of the 2022 IEEE European Test Symposium (ETS)., 9810436, IEEE, Danvers, pp. 1-6, 2022 IEEE European Test Symposium (ETS), Barcelona, Spain, 23/05/22. https://doi.org/10.1109/ETS54262.2022.9810436

TY - GEN

T1 - PVT Analysis for RRAM and STT-MRAM-based Logic Computation-in-Memory

AU - Fieback, Moritz

AU - Münch, Christopher

AU - Gebregiorgis, Anteneh

AU - Cardoso Medeiros, Guilherme

AU - Taouil, Mottaqiallah

AU - Hamdioui, Said

AU - Tahoori, Mehdi

N1 - Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.

PY - 2022

Y1 - 2022

N2 - Emerging non-volatile resistive memories like Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) and Resistive RAM (RRAM) are in the focus of today’s research. They offer promising alternative computing architectures such as computation-in-memory (CiM) to reduce the transfer overhead between CPU and memory, usually referred to as the memory wall, which is present in all von Neumann architectures. A multitude of architectures with CiM capabilities are based on these devices, due to their inherent resistive behavior and thus their ability to perform calculation directly within the memory, and thus without invoking the CPU at all. However, emerging memories are sensitive to Process, Voltage and Temperature (PVT) variations. This sensitivity has an even larger impact on CiM architectures. In this paper, we analyze and compare the impact of PVT variations on STT-MRAM and RRAM-based CiM architectures. We perform a sensitivity analysis to identify which parts of the CiM structure are most susceptible to PVT variations, for each technology. Based on these analyses, we recommend that STT-MRAM is used in high-performance CiM, while RRAM is used for edge CiM.

AB - Emerging non-volatile resistive memories like Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) and Resistive RAM (RRAM) are in the focus of today’s research. They offer promising alternative computing architectures such as computation-in-memory (CiM) to reduce the transfer overhead between CPU and memory, usually referred to as the memory wall, which is present in all von Neumann architectures. A multitude of architectures with CiM capabilities are based on these devices, due to their inherent resistive behavior and thus their ability to perform calculation directly within the memory, and thus without invoking the CPU at all. However, emerging memories are sensitive to Process, Voltage and Temperature (PVT) variations. This sensitivity has an even larger impact on CiM architectures. In this paper, we analyze and compare the impact of PVT variations on STT-MRAM and RRAM-based CiM architectures. We perform a sensitivity analysis to identify which parts of the CiM structure are most susceptible to PVT variations, for each technology. Based on these analyses, we recommend that STT-MRAM is used in high-performance CiM, while RRAM is used for edge CiM.

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KW - emerging memories

KW - STT-MRAM

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KW - reliability

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U2 - 10.1109/ETS54262.2022.9810436

DO - 10.1109/ETS54262.2022.9810436

M3 - Conference contribution

SN - 978-1-6654-6707-0

SP - 1

EP - 6

BT - Proceedings of the 2022 IEEE European Test Symposium (ETS)

PB - IEEE

CY - Danvers

T2 - 2022 IEEE European Test Symposium (ETS)

Y2 - 23 May 2022 through 27 May 2022

ER -

PVT Analysis for RRAM and STT-MRAM-based Logic Computation-in-Memory

Abstract

Conference

Bibliographical note

Keywords

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