Rapid Design-Space Exploration for Low-Power Manycores under Process Variation utilizing Machine Learning

Sohaib Majzoub*, Resve A. Saleh, Mottaqiallah Taouil, Said Hamdioui, Mohamed Bamakhrama

*Corresponding author for this work

Research output: Contribution to journalArticleScientificpeer-review

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Abstract

Design-space exploration for low-power manycore design is a daunting and time-consuming task which requires some complex tools and frameworks to achieve. In the presence of process variation, the problem becomes even more challenging, especially the time associated with trial-and-error selection of the proper options in the tools to obtain the optimal power dissipation. The key contribution of this work is the novel use of machine learning to speed up the design process by embedding the tool expertise needed for low power design-space exploration for manycores into a trained neural network. To enable this, we first generate a large volume of data for 36000 benchmark applications by running them under all possible configurations to find the optimal one in terms of power. This is done using our own tool called LVSiM, a holistic manycore optimization program including process variations. A neural network is trained with this information to build in the expertise. A second contribution of this work is to define a new set of features, relevant to power and performance optimization, when training the neural network. At design time, the trained neural network is used to select the proper options on behalf of the user based on the features of any new application. However, one problem encountered with this approach is that the database constructed for machine learning has many outliers due to randomness associated with process variation which creates a major headache for classification - the supervised learning task performed by neural networks. The third key contribution of this work is a novel data coercion algorithm used as a corrective measure to handle the outliers. The proposed data coercion scheme produces results that are within 3.9% of the optimal power consumption compared to 7% without data coercion. Furthermore, the proposed method is about an order of magnitude faster than a heuristic approach and two orders of magnitude faster than a brute-force approach for design-space exploration.
Original languageEnglish
Article number9810244
Pages (from-to)70187-70203
Number of pages17
JournalIEEE Access
Volume10
DOIs
Publication statusPublished - 2022

Keywords

  • Neural Network
  • Simulator
  • manycore
  • low-power
  • process variation
  • frequency scaling
  • voltage scaling
  • 3D-Stack
  • voltage selection
  • within-die variation

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