Reconfigurable universal SAD-multiplier array

H Calderón, S Vassiliadis

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific


In this paper, we investigate the collapsing of some multi-operand addition related operations into a single array. More specifically we consider multiplication and Sum of Absolute Differences (SAD) and propose an array capable of performing the aforementioned operations for unsigned, signed magnitude, and two's complement notations. The array, called a universal array, is divided into common and controlled logic blocks intended to be reconfigured dynamically. The proposed unit was constructed a ... Keywords: binary multiplication, partial reconfiguration, reconfigurable computing, sum of absolute differences
Original languageUndefined/Unknown
Title of host publicationProceedings of the 2nd conference on computing frontiers
Editors s.n.
Place of PublicationNew York
PublisherAssociation for Computing Machinery (ACM)
Number of pages5
ISBN (Print)1-59593-019-1
Publication statusPublished - 2005
Event2nd conference on Computing frontiers, Ischia, Italy - New York
Duration: 4 May 20056 May 2005

Publication series



Conference2nd conference on Computing frontiers, Ischia, Italy

Bibliographical note

editors onbekend, sb


  • conference contrib. refereed
  • Conf.proc. > 3 pag

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