In this paper, we investigate the collapsing of some multi-operand addition related operations into a single array. More specifically we consider multiplication and Sum of Absolute Differences (SAD) and propose an array capable of performing the aforementioned operations for unsigned, signed magnitude, and two's complement notations. The array, called a universal array, is divided into common and controlled logic blocks intended to be reconfigured dynamically. The proposed unit was constructed a ...
Keywords: binary multiplication, partial reconfiguration, reconfigurable computing, sum of absolute differences
|Conference||2nd conference on Computing frontiers, Ischia, Italy|
|Period||4/05/05 → 6/05/05|
editors onbekend, sb
- conference contrib. refereed
- Conf.proc. > 3 pag