Reconfigurable universal SAD-multiplier array

H Calderón; S Vassiliadis

doi:http://doi.acm.org/10.1145/1062261.1062277

Reconfigurable universal SAD-multiplier array

H Calderón, S Vassiliadis

Computer Engineering

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific

Abstract

In this paper, we investigate the collapsing of some multi-operand addition related operations into a single array. More specifically we consider multiplication and Sum of Absolute Differences (SAD) and propose an array capable of performing the aforementioned operations for unsigned, signed magnitude, and two's complement notations. The array, called a universal array, is divided into common and controlled logic blocks intended to be reconfigured dynamically. The proposed unit was constructed a ... Keywords: binary multiplication, partial reconfiguration, reconfigurable computing, sum of absolute differences

Original language	Undefined/Unknown
Title of host publication	Proceedings of the 2nd conference on computing frontiers
Editors	s.n.
Place of Publication	New York
Publisher	Association for Computing Machinery (ACM)
Pages	72-76
Number of pages	5
ISBN (Print)	1-59593-019-1
DOIs	https://doi.org/http://doi.acm.org/10.1145/1062261.1062277
Publication status	Published - 2005
Event	2nd conference on Computing frontiers, Ischia, Italy - New York Duration: 4 May 2005 → 6 May 2005

Publication series

Name
Publisher	ACM

Conference

Conference	2nd conference on Computing frontiers, Ischia, Italy
Period	4/05/05 → 6/05/05

Bibliographical note

editors onbekend, sb

Keywords

conference contrib. refereed
Conf.proc. > 3 pag

Access to Document

http://doi.acm.org/10.1145/1062261.1062277

Cite this

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title = "Reconfigurable universal SAD-multiplier array",

abstract = "In this paper, we investigate the collapsing of some multi-operand addition related operations into a single array. More specifically we consider multiplication and Sum of Absolute Differences (SAD) and propose an array capable of performing the aforementioned operations for unsigned, signed magnitude, and two's complement notations. The array, called a universal array, is divided into common and controlled logic blocks intended to be reconfigured dynamically. The proposed unit was constructed a ... Keywords: binary multiplication, partial reconfiguration, reconfigurable computing, sum of absolute differences",

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AB - In this paper, we investigate the collapsing of some multi-operand addition related operations into a single array. More specifically we consider multiplication and Sum of Absolute Differences (SAD) and propose an array capable of performing the aforementioned operations for unsigned, signed magnitude, and two's complement notations. The array, called a universal array, is divided into common and controlled logic blocks intended to be reconfigured dynamically. The proposed unit was constructed a ... Keywords: binary multiplication, partial reconfiguration, reconfigurable computing, sum of absolute differences

KW - conference contrib. refereed

KW - Conf.proc. > 3 pag

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