Research On FOPLP Package of multi-chip Power Module

Jing Jiang, Jia ren Huo, Guan qiang Song, Huaiyu Ye, De Bo Liu, Guoqi Zhang

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

Abstract

Power devices are developing for the small volume, high performance and modularization. With more and more application scenarios of Brushless Direct Current Motor (BLDC), MOSFET multi-chip module (MCM) is popular with people. However, the conventional wire Bonding and Copper clip welding technology struggles to meet the requirements for the excessive heat accumulation and complex logic problems in MCM. While the above problems can be well solved by using the new Fan out panel level packing(FOPLP) technology for QFN packaging of multi-chip. The traditional welding technology is used at the bottom of the chip, and the copper porous link is used at the top of the chip with low parasitic capacitance, inductance and low Rdson in electrical performance. In respect to thermal management, the ?JC on the top of the chip can be reduced, which has the effect of double-sided heat dissipation. Top Layer interconnection technology is adopted in the packaging scheme, which can have complex circuit layout.This paper mainly describes the technical implementation of this packaging technology, adopting the finite element software to establish a three-dimensional model of a new type of FOPLP and wire welding packaging for MCM. The thermal resistance of different packaging schemes is calculated to confirm the advantages and disadvantages of different schemes by the way of thermal simulation, the internal temperature distribution of different packaging structures and the main influencing factors of the thermal resistance of packaging compared.

Original languageEnglish
Title of host publicationProceedings - 2020 IEEE 8th Electronics System-Integration Technology Conference, ESTC 2020
PublisherIEEE
Pages1-6
Number of pages6
ISBN (Electronic)978-1-7281-6293-5
ISBN (Print)978-1-7281-6294-2
DOIs
Publication statusPublished - 2020
EventESTC 2020: IEEE 8th Electronics System-Integration Technology Conference - Tønsberg, Norway
Duration: 15 Sep 202018 Sep 2020
Conference number: 8th

Publication series

NameProceedings - 2020 IEEE 8th Electronics System-Integration Technology Conference, ESTC 2020

Conference

ConferenceESTC 2020
CountryNorway
CityTønsberg
Period15/09/2018/09/20

Keywords

  • FOPLP
  • Internal resistance
  • MCM
  • Power devices
  • Thermal simulation

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