Review of Manufacturing Process Defects and Their Effects on Memristive Devices

L. M.Bolzani Poehls*, M. C.R. Fieback, S. Hoffmann-Eifert, T. Copetti, E. Brum, S. Menzel, S. Hamdioui, T. Gemmeke

*Corresponding author for this work

Research output: Contribution to journalArticleScientificpeer-review

6 Citations (Scopus)
128 Downloads (Pure)

Abstract

Complementary Metal Oxide Semiconductor (CMOS) technology has been scaled down over the last forty years making possible the design of high-performance applications, following the predictions made by Gordon Moore and Robert H. Dennard in the 1970s. However, there is a growing concern that device scaling, while maintaining cost-effective production, will become infeasible below a certain feature size. In parallel, emerging applications including Internet-of-Things (IoT) and big data applications present high demands in terms of storage and computing capability, combined with challenging constraints in terms of size, power consumption and response latency. In this scenario, memristive devices have become promising candidates to complement the CMOS technology due to their CMOS manufacturing process compatibility, great scalability and high density, zero standby power consumption and their capacity to implement high density memories as well as new computing paradigms. Despite these advantages, memristive devices are also susceptible to manufacturing defects that may cause unique faulty behaviors that are not seen in CMOS, increasing significantly the complexity of test procedures. This paper provides a review about the manufacturing process of memristives devices, focusing on Valence Change Mechanism (VCM)-based memristive devices, and a comparative analysis of the CMOS and memristive device manufacturing processes. Moreover, this paper identifies possible manufacturing failure mechanisms that may affect these novel devices, completing the list of the already known mechanisms, and provides a discussion about possible faulty behaviors. Note that the identification of these mechanisms provides insights regarding the possible memristive devices’ defective behaviors, enabling to derive more accurate fault models and consequently, more suitable test procedures.

Original languageEnglish
Pages (from-to)427-437
Number of pages11
JournalJournal of Electronic Testing: Theory and Applications (JETTA)
Volume37
Issue number4
DOIs
Publication statusPublished - 2021

Keywords

  • CMOS
  • Defects
  • Fault models
  • Manufacturing process
  • Memristive devices

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