A cost-effective add-on process module for reducing ohmic losses of radio-frequency (RF) inductors and interconnects in RF/BiCMOS and RF/CMOS technologies built on CMOS logic processes is proposed. The module is based on the local thickening of the top metal layer of the thin CMOS interconnects through copper (Cu) electroplating in selected areas. The combination of dense Cu-interconnects in the CMOS logic sections, of thick Cu top-level wiring through local Cu electroplating in the RF sections, and of aluminum (Al) capping of the bond pads provides an optimum tradeoff between packaging requirements, quality of passive components and interconnects, and cost. A special wet-etch process sequence for removal of the Cu-seed and adhesion films from the exposed top metal layer is described. A record quality factor of /spl sim/13 for a 10-nH inductor on a conventional 5-/spl Omega/-cm silicon substrate is demonstrated.
|Number of pages||7|
|Journal||IEEE Transactions on Electron Devices|
|Publication status||Published - 2004|
- academic journal papers
- ZX CWTS 1.00 <= JFIS < 3.00