Shortest path reduction in a class of uniform fault tolerant networks

PD Joshi; S Hamdioui

doi:10.1109/DFT.2014.6962102

Shortest path reduction in a class of uniform fault tolerant networks

Computer Engineering

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

Original language	English
Title of host publication	Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Editors	M Ottavi, S Hamdioui
Place of Publication	Piscataway, NJ, USA
Publisher	IEEE
Pages	234-239
Number of pages	6
ISBN (Print)	978-1-4799-6154-2
DOIs	https://doi.org/10.1109/DFT.2014.6962102
Publication status	Published - 2014
Event	DFT 2014, Amsterdam, Netherlands - Piscataway, NJ, USA Duration: 1 Oct 2014 → 3 Oct 2014

Publication series

Name
Publisher	IEEE

Conference

Conference	DFT 2014, Amsterdam, Netherlands
Period	1/10/14 → 3/10/14

Bibliographical note

Harvest

Access to Document

10.1109/DFT.2014.6962102

Cite this

@inproceedings{bcf939d0e982433bbaba4059a2819151,

title = "Shortest path reduction in a class of uniform fault tolerant networks",

author = "PD Joshi and S Hamdioui",

note = "Harvest; DFT 2014, Amsterdam, Netherlands ; Conference date: 01-10-2014 Through 03-10-2014",

year = "2014",

doi = "10.1109/DFT.2014.6962102",

language = "English",

isbn = "978-1-4799-6154-2",

publisher = "IEEE",

pages = "234--239",

editor = "M Ottavi and S Hamdioui",

booktitle = "Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)",

address = "United States",

}

Joshi, PD & Hamdioui, S 2014, Shortest path reduction in a class of uniform fault tolerant networks. in M Ottavi & S Hamdioui (eds), Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT). IEEE, Piscataway, NJ, USA, pp. 234-239, DFT 2014, Amsterdam, Netherlands, 1/10/14. https://doi.org/10.1109/DFT.2014.6962102

Shortest path reduction in a class of uniform fault tolerant networks. / Joshi, PD; Hamdioui, S.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT). ed. / M Ottavi; S Hamdioui. Piscataway, NJ, USA: IEEE, 2014. p. 234-239.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

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AU - Joshi, PD

AU - Hamdioui, S

N1 - Harvest

PY - 2014

Y1 - 2014

U2 - 10.1109/DFT.2014.6962102

DO - 10.1109/DFT.2014.6962102

M3 - Conference contribution

SN - 978-1-4799-6154-2

SP - 234

EP - 239

BT - Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

A2 - Ottavi, M

A2 - Hamdioui, S

PB - IEEE

CY - Piscataway, NJ, USA

T2 - DFT 2014, Amsterdam, Netherlands

Y2 - 1 October 2014 through 3 October 2014

ER -