Silicon/silicon-germanium heterostructures for spin-qubit quantum processors

Research output: ThesisDissertation (TU Delft)

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Spin qubits in silicon have emerged as a promising candidate for a scalable quantum computer due to their small footprint, long coherence times, and their compatibility with advanced semiconductor manufacturing. However, all known spin qubit material hosts come with specific challenges, that limit the performance of quantum information processing. In this thesis we study Si/SiGe heterostructures, comprising a strained silicon (Si) quantum well which is sandwiched between two silicon-germanium (SiGe) barriers. Si/SiGe heterostructures designed to act as solid-state matrix to host spin qubits have three intrinsic material challenges that limit performance: hyperfine interaction, valley splitting, and charge noise. Therefore, to realize a scalable quantum computer in Si/SiGe heterostructures we first quantify the performance limiting parameters and subsequently, we improve them systematically with statistical significance.

Acquiring data with statistical significance, however proves challenging for quantum devices in Si/SiGe heterostructures due to complicated and time-consuming fabrication schemes for device manufacturing, and the need of using dilution refrigerators that cool samples down to sub-Kelvin temperatures with only a limited amount of wires for electrical characterization of devices. Therefore, in this thesis we demonstrate fast growth-fabrication-measurement feedback cycles to accelerate our understanding on the materials and devices.

We realize such fast feedback cycles by first establishing a unique workflow at TU Delft, allowing 100~mm wafer growth and fabrication. Subsequently in our first experiment, we overcome the wiring bottleneck by presenting a cryogenic multiplexing platform that multiplies DC wires inside of a dilution refrigerator. This cryogenic multiplexer platform uses commercially available CMOS components, is compatible with any dilution refrigerator, and allows us to measure thirteen chips in the same cooldown at a temperature of 50~mK and at magnetic fields of up to 10~T. We confirm these extreme measurement conditions by showing statistically significant quantum transport properties of industrially grown 300~mm $^{\text{nat}}$Si/SiGe wafers.

In the following experimental chapters we then leverage the cryogenic multiplexer to successively tackle the performance limiting parameters of spin qubit processors in Si/SiGe heterostructures. In the second experiment we first analyze valley splitting in two dimensional electron gases and observe that valley splitting increases linearly with the electric field at the quantum Hall edge states of the device at a rate consistent with theoretical predictions. In turn, this observation allows us to evaluate valley splitting on a micron length scale with relatively simple Hall-bar measurements.

In the third experiment we show two major improvements in our heterostructures. First, we measure valley splitting in quantum dots with varying quantum well interface sharpness with statistical significance. We then proceed to analyze the atomic composition of the quantum well interfaces in several samples using atom probe tomography and show that Ge atoms are distributed randomly in each atomic layer. Subsequently using the atom probe tomography results as input, we simulate valley splitting and show that valley splitting depends on the atomistic details of the interface and needs to be treated as a statistical distribution. We then propose a strategy to increase valley splitting on average above a chosen threshold by introducing a small concentration of Ge atoms into the quantum well. Second, all electrical measurements in this experiment are performed in isotopically purified $^{28}$Si quantum wells, which reduces the hyperfine interaction and hence increases qubit coherence times. While we do not explicitly discuss this improvement in this chapter, it is a crucial baseline for all following experiments in this thesis and for all qubit experiments using Delft grown $^{28}$Si/SiGe heterostructures.

We then move to show wafer-scale improvements of the disorder landscape of Si quantum wells in our fourth experiment. There, we challenge the common approach of growing an epitaxial Si cap on the $^{28}$Si/SiGe heterostructure, by replacing the Si cap with an amorphous Si-rich layer. We compare these two heterostructues by monitoring the statistical performance of mobility, percolation density, maximum electric field before hysteresis, and single particle relaxation time and observe a statistical performance increase of the mean value and the standard deviation.

In the fifth experiment we study a heterostructure with a thin quantum well and compare its statistical performance of mobility, percolation density, and charge noise with the performance of the heterostructures from the preceding experiment. Importantly, we find that misfit dislocation arising from strain relaxation are significantly reduced in thin quantum wells as confirmed by geometrical phase analysis of transmission-electron microscope images. In consequence, we observe a statistical performance increase of all key metrics in the novel heterostructure, only possible by our approach of engineering the critical material layers. Finally, we see promising simulated qubit coherence times and qubit error rates when using our charge noise results as simulation input, hinting at a practical advantage of our novel $^{28}$Si/SiGe heterostructures for quantum processors.

In the last experimental chapter we demonstrate how our improved $^{28}$Si/SiGe heterostructures have enabled two key experiments in the field of spin-based quantum computing. First, we show that our purified heterostrucures may host high-quality qubits, that in turn serve as a testbed for demonstrating CMOS-based cryogenic control of silicon quantum circuits. Second, we show how our isotopically purified, low-disorder heterostructures host a 6-qubit quantum processor with high-fidelity initialization, high-fidelity gate operation, and high-fidelity readout.

We conclude this thesis by highlighting key improvements of our $^{28}$Si/SiGe hetero-structures that have contributed to state-of-the-art spin qubit experiments. However, our heterostructures still require further improvements if we want to achieve error rates around 10$^{-6}$ and scale to large spin qubit arrays with more than a million qubits. Therefore, we discuss additional material changes that could further lower spin qubit error rates and we consider how to assess the uniformity of the material over different length scales, relevant when striving for larger qubit arrays.
Original languageEnglish
QualificationDoctor of Philosophy
Awarding Institution
  • Delft University of Technology
  • Vandersypen, L.M.K., Supervisor
  • Scappucci, G., Supervisor
Award date7 Dec 2022
Print ISBNs978-90-8593-546-9
Publication statusPublished - 2022


  • Silicon quantum wells
  • valley splitting
  • charge noise
  • quantum dots
  • quantum processors
  • Hall effect
  • quantumHall effect


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