Simultaneous reconfiguration of issue-width and instruction cache for a VLIW processor

F Anjam; L Carro; JSSM Wong; GL Nazar; MB Rutzig

Simultaneous reconfiguration of issue-width and instruction cache for a VLIW processor

F Anjam, L Carro, JSSM Wong, GL Nazar, MB Rutzig

Computer Engineering

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

5 Citations (Scopus)

Original language	English
Title of host publication	International conference on embedded computer systems: architecture modeling and simulation
Editors	s.n.
Place of Publication	New York
Publisher	IEEE Society
Pages	1-10
Number of pages	10
Publication status	Published - 2012
Event	IC-SAMOS 2012 - New York Duration: 16 Jul 2012 → 19 Jul 2012

Publication series

Name
Publisher	IEEE

Conference

Conference	IC-SAMOS 2012
Period	16/07/12 → 19/07/12

Cite this

@inproceedings{f6e8cc9d12314ab7bf2460dee32e1538,

title = "Simultaneous reconfiguration of issue-width and instruction cache for a VLIW processor",

author = "F Anjam and L Carro and JSSM Wong and GL Nazar and MB Rutzig",

year = "2012",

language = "English",

publisher = "IEEE Society",

pages = "1--10",

editor = "s.n.",

booktitle = "International conference on embedded computer systems: architecture modeling and simulation",

note = "IC-SAMOS 2012 ; Conference date: 16-07-2012 Through 19-07-2012",

}

Simultaneous reconfiguration of issue-width and instruction cache for a VLIW processor. / Anjam, F; Carro, L; Wong, JSSM et al.

International conference on embedded computer systems: architecture modeling and simulation. ed. / s.n. New York : IEEE Society, 2012. p. 1-10.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

T1 - Simultaneous reconfiguration of issue-width and instruction cache for a VLIW processor

AU - Anjam, F

AU - Carro, L

AU - Wong, JSSM

AU - Nazar, GL

AU - Rutzig, MB

PY - 2012

Y1 - 2012

UR - http://ce-publications.et.tudelft.nl/publications/144_simultaneous_reconfiguration_of_issuewidth_and_instruction.pdf

M3 - Conference contribution

SP - 1

EP - 10

BT - International conference on embedded computer systems: architecture modeling and simulation

A2 - s.n., null

PB - IEEE Society

CY - New York

T2 - IC-SAMOS 2012

Y2 - 16 July 2012 through 19 July 2012

ER -

Simultaneous reconfiguration of issue-width and instruction cache for a VLIW processor

Publication series

Conference

Other files and links

Cite this