Single-grain Si TFTs with ECR-PECVD gate SiO2

R Ishihara; Y Hiroshima; D Abe; BD van Dijk; PC van der Wilt; S Higashi; S Inoue; T Shimoda; JW Metselaar; CIM Beenakker

Single-grain Si TFTs with ECR-PECVD gate SiO2

R Ishihara, Y Hiroshima, D Abe, BD van Dijk, PC van der Wilt, S Higashi, S Inoue, T Shimoda, JW Metselaar, CIM Beenakker

Electronic Components, Technology and Materials

Research output: Contribution to journal › Article › Scientific › peer-review

33 Citations (Scopus)

Abstract

High-performance Si thin-film transistors (TFTs) are fabricated inside a single, location-controlled grain with gate SiO/sub 2/ deposited by electron cyclotron resonance plasma enhanced chemical vapor deposition (ECR-PECVD). The position of the large grains is controlled by /spl mu/-Czochralski (grain-filter) process with excimer-laser crystallization. Owing to the low interface trap density of ECR-PECVD SiO/sub 2/ the single-grain Si TFTs showed a smaller subthreshold swing of 0.45 V/decade, in addition to a higher field-effect mobility for electrons of 460 cm/sup 2//Vs than that with low-pressure chemical-vapor deposited (LPCVD) SiO/sub 2/.

Original language	Undefined/Unknown
Pages (from-to)	500-502
Number of pages	3
Journal	IEEE Transactions on Electron Devices
Volume	51
Issue number	3
Publication status	Published - 2004

Keywords

academic journal papers
ZX CWTS 1.00 <= JFIS < 3.00

Cite this

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title = "Single-grain Si TFTs with ECR-PECVD gate SiO2",

abstract = "High-performance Si thin-film transistors (TFTs) are fabricated inside a single, location-controlled grain with gate SiO/sub 2/ deposited by electron cyclotron resonance plasma enhanced chemical vapor deposition (ECR-PECVD). The position of the large grains is controlled by /spl mu/-Czochralski (grain-filter) process with excimer-laser crystallization. Owing to the low interface trap density of ECR-PECVD SiO/sub 2/ the single-grain Si TFTs showed a smaller subthreshold swing of 0.45 V/decade, in addition to a higher field-effect mobility for electrons of 460 cm/sup 2//Vs than that with low-pressure chemical-vapor deposited (LPCVD) SiO/sub 2/.",

keywords = "academic journal papers, ZX CWTS 1.00 <= JFIS < 3.00",

author = "R Ishihara and Y Hiroshima and D Abe and {van Dijk}, BD and {van der Wilt}, PC and S Higashi and S Inoue and T Shimoda and JW Metselaar and CIM Beenakker",

year = "2004",

language = "Undefined/Unknown",

volume = "51",

pages = "500--502",

journal = "IEEE Transactions on Electron Devices",

issn = "0018-9383",

publisher = "IEEE",

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TY - JOUR

T1 - Single-grain Si TFTs with ECR-PECVD gate SiO2

AU - Ishihara, R

AU - Hiroshima, Y

AU - Abe, D

AU - van Dijk, BD

AU - van der Wilt, PC

AU - Higashi, S

AU - Inoue, S

AU - Shimoda, T

AU - Metselaar, JW

AU - Beenakker, CIM

PY - 2004

Y1 - 2004

N2 - High-performance Si thin-film transistors (TFTs) are fabricated inside a single, location-controlled grain with gate SiO/sub 2/ deposited by electron cyclotron resonance plasma enhanced chemical vapor deposition (ECR-PECVD). The position of the large grains is controlled by /spl mu/-Czochralski (grain-filter) process with excimer-laser crystallization. Owing to the low interface trap density of ECR-PECVD SiO/sub 2/ the single-grain Si TFTs showed a smaller subthreshold swing of 0.45 V/decade, in addition to a higher field-effect mobility for electrons of 460 cm/sup 2//Vs than that with low-pressure chemical-vapor deposited (LPCVD) SiO/sub 2/.

AB - High-performance Si thin-film transistors (TFTs) are fabricated inside a single, location-controlled grain with gate SiO/sub 2/ deposited by electron cyclotron resonance plasma enhanced chemical vapor deposition (ECR-PECVD). The position of the large grains is controlled by /spl mu/-Czochralski (grain-filter) process with excimer-laser crystallization. Owing to the low interface trap density of ECR-PECVD SiO/sub 2/ the single-grain Si TFTs showed a smaller subthreshold swing of 0.45 V/decade, in addition to a higher field-effect mobility for electrons of 460 cm/sup 2//Vs than that with low-pressure chemical-vapor deposited (LPCVD) SiO/sub 2/.

KW - academic journal papers

KW - ZX CWTS 1.00 <= JFIS < 3.00

M3 - Article

SN - 0018-9383

VL - 51

SP - 500

EP - 502

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

IS - 3

ER -