High-performance Si thin-film transistors (TFTs) are fabricated inside a single, location-controlled grain with gate SiO/sub 2/ deposited by electron cyclotron resonance plasma enhanced chemical vapor deposition (ECR-PECVD). The position of the large grains is controlled by /spl mu/-Czochralski (grain-filter) process with excimer-laser crystallization. Owing to the low interface trap density of ECR-PECVD SiO/sub 2/ the single-grain Si TFTs showed a smaller subthreshold swing of 0.45 V/decade, in addition to a higher field-effect mobility for electrons of 460 cm/sup 2//Vs than that with low-pressure chemical-vapor deposited (LPCVD) SiO/sub 2/.
|Number of pages||3|
|Journal||IEEE Transactions on Electron Devices|
|Publication status||Published - 2004|
- academic journal papers
- ZX CWTS 1.00 <= JFIS < 3.00