Abstract
STT-MRAM has long been a promising non-volatile memory solution for the embedded application space owing to its attractive characteristics such as non-volatility, low leakage, high endurance, and scalability. However, the operating requirements for high-performance computing (HPC) and low power (LP) applications involve different challenges. This paper addresses different aspects of STT-MRAM; it will cover state-of-the-art, some new results and future challenges related to technology, design and test. While STT-MRAM devices have shown encouraging performance metrics at device-level, a key challenge has been achieving backend-of-line (BEOL) CMOS compatibility, while retaining the benefits of low power operation. Scaling demands to improve data densities have placed additional challenges in terms of addressing the impact of process-induced damage on device performance at CD < 100 nm. In addition, the paper discusses the design of reliable read mechanism considering the variability effects. Moreover, the failure of traditional fault modeling and test approaches in model STT-MRAM unique defects for appropriate test solutions is demonstrated in this paper based on silicon data.
Original language | English |
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Title of host publication | Proceedings - of the 2022 IEEE 40th VLSI Test Symposium, VTS 2022 |
Publisher | IEEE |
Number of pages | 10 |
ISBN (Electronic) | 978-1-6654-1060-1 |
ISBN (Print) | 978-1-6654-1061-8 |
DOIs | |
Publication status | Published - 2022 |
Event | 40th IEEE VLSI Test Symposium, VTS 2022 - Virtual, Online, United States Duration: 25 Apr 2022 → 27 Apr 2022 |
Conference
Conference | 40th IEEE VLSI Test Symposium, VTS 2022 |
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Country/Territory | United States |
City | Virtual, Online |
Period | 25/04/22 → 27/04/22 |
Bibliographical note
Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-careOtherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.
Keywords
- Device-aware test
- Reliability
- STT-MRAM