Special Session: STT-MRAMs: Technology, Design and Test

Anteneh Gebregiorgis, Lizhou Wu, Christopher Münch, Siddharth Rao, Mehdi B. Tahoori, Said Hamdioui

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

Abstract

STT-MRAM has long been a promising non-volatile memory solution for the embedded application space owing to its attractive characteristics such as non-volatility, low leakage, high endurance, and scalability. However, the operating requirements for high-performance computing (HPC) and low power (LP) applications involve different challenges. This paper addresses different aspects of STT-MRAM; it will cover state-of-the-art, some new results and future challenges related to technology, design and test. While STT-MRAM devices have shown encouraging performance metrics at device-level, a key challenge has been achieving backend-of-line (BEOL) CMOS compatibility, while retaining the benefits of low power operation. Scaling demands to improve data densities have placed additional challenges in terms of addressing the impact of process-induced damage on device performance at CD < 100 nm. In addition, the paper discusses the design of reliable read mechanism considering the variability effects. Moreover, the failure of traditional fault modeling and test approaches in model STT-MRAM unique defects for appropriate test solutions is demonstrated in this paper based on silicon data.

Original languageEnglish
Title of host publicationProceedings - of the 2022 IEEE 40th VLSI Test Symposium, VTS 2022
PublisherIEEE
Number of pages10
ISBN (Electronic)978-1-6654-1060-1
ISBN (Print)978-1-6654-1061-8
DOIs
Publication statusPublished - 2022
Event40th IEEE VLSI Test Symposium, VTS 2022 - Virtual, Online, United States
Duration: 25 Apr 202227 Apr 2022

Conference

Conference40th IEEE VLSI Test Symposium, VTS 2022
Country/TerritoryUnited States
CityVirtual, Online
Period25/04/2227/04/22

Keywords

  • Device-aware test
  • Reliability
  • STT-MRAM

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